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Re: [PATCH v3 3/6] target/riscv: Introduce privilege version field in th
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From: |
Atish Patra |
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Subject: |
Re: [PATCH v3 3/6] target/riscv: Introduce privilege version field in the CSR ops. |
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Date: |
Tue, 22 Feb 2022 12:37:39 -0800 |
On Mon, Feb 21, 2022 at 1:42 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Sun, Feb 6, 2022 at 7:19 PM Atish Patra <atishp@rivosinc.com> wrote:
> >
> > To allow/disallow the CSR access based on the privilege spec, a new field
> > in the csr_ops is introduced. It also adds the privileged specification
> > version (v1.12) for the CSRs introduced in the v1.12. This includes the
> > new ratified extensions such as Vector, Hypervisor and secconfig CSR.
> >
> > Signed-off-by: Atish Patra <atishp@rivosinc.com>
>
> It might be worth mentioning that there is no enforcement in this commit
>
Sure. I will update the commit text and send a v4.
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>
> Alistair
>
> > ---
> > target/riscv/cpu.h | 2 +
> > target/riscv/csr.c | 103 ++++++++++++++++++++++++++++++---------------
> > 2 files changed, 70 insertions(+), 35 deletions(-)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index 60b847141db2..0741f9822cf0 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -593,6 +593,8 @@ typedef struct {
> > riscv_csr_op_fn op;
> > riscv_csr_read128_fn read128;
> > riscv_csr_write128_fn write128;
> > + /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0)
> > */
> > + uint32_t min_priv_ver;
> > } riscv_csr_operations;
> >
> > /* CSR function table constants */
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 8c63caa39245..25a0df498669 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -2981,13 +2981,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > [CSR_FRM] = { "frm", fs, read_frm, write_frm },
> > [CSR_FCSR] = { "fcsr", fs, read_fcsr, write_fcsr },
> > /* Vector CSRs */
> > - [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart },
> > - [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat },
> > - [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm },
> > - [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr },
> > - [CSR_VL] = { "vl", vs, read_vl },
> > - [CSR_VTYPE] = { "vtype", vs, read_vtype },
> > - [CSR_VLENB] = { "vlenb", vs, read_vlenb },
> > + [CSR_VSTART] = { "vstart", vs, read_vstart, write_vstart,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_VXSAT] = { "vxsat", vs, read_vxsat, write_vxsat,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_VXRM] = { "vxrm", vs, read_vxrm, write_vxrm,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_VCSR] = { "vcsr", vs, read_vcsr, write_vcsr,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_VL] = { "vl", vs, read_vl,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_VTYPE] = { "vtype", vs, read_vtype,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_VLENB] = { "vlenb", vs, read_vlenb,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > /* User Timers and Counters */
> > [CSR_CYCLE] = { "cycle", ctr, read_instret },
> > [CSR_INSTRET] = { "instret", ctr, read_instret },
> > @@ -3096,33 +3103,58 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > [CSR_SIEH] = { "sieh", aia_smode32, NULL, NULL, rmw_sieh },
> > [CSR_SIPH] = { "siph", aia_smode32, NULL, NULL, rmw_siph },
> >
> > - [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus,
> > write_hstatus },
> > - [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg,
> > write_hedeleg },
> > - [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL,
> > rmw_hideleg },
> > - [CSR_HVIP] = { "hvip", hmode, NULL, NULL,
> > rmw_hvip },
> > - [CSR_HIP] = { "hip", hmode, NULL, NULL,
> > rmw_hip },
> > - [CSR_HIE] = { "hie", hmode, NULL, NULL,
> > rmw_hie },
> > - [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren,
> > write_hcounteren },
> > - [CSR_HGEIE] = { "hgeie", hmode, read_hgeie,
> > write_hgeie },
> > - [CSR_HTVAL] = { "htval", hmode, read_htval,
> > write_htval },
> > - [CSR_HTINST] = { "htinst", hmode, read_htinst,
> > write_htinst },
> > - [CSR_HGEIP] = { "hgeip", hmode, read_hgeip, NULL
> > },
> > - [CSR_HGATP] = { "hgatp", hmode, read_hgatp,
> > write_hgatp },
> > - [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta,
> > write_htimedelta },
> > - [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah,
> > write_htimedeltah },
> > -
> > - [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus,
> > write_vsstatus },
> > - [CSR_VSIP] = { "vsip", hmode, NULL, NULL,
> > rmw_vsip },
> > - [CSR_VSIE] = { "vsie", hmode, NULL, NULL,
> > rmw_vsie },
> > - [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec,
> > write_vstvec },
> > - [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch,
> > write_vsscratch },
> > - [CSR_VSEPC] = { "vsepc", hmode, read_vsepc,
> > write_vsepc },
> > - [CSR_VSCAUSE] = { "vscause", hmode, read_vscause,
> > write_vscause },
> > - [CSR_VSTVAL] = { "vstval", hmode, read_vstval,
> > write_vstval },
> > - [CSR_VSATP] = { "vsatp", hmode, read_vsatp,
> > write_vsatp },
> > -
> > - [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2,
> > write_mtval2 },
> > - [CSR_MTINST] = { "mtinst", hmode, read_mtinst,
> > write_mtinst },
> > + [CSR_HSTATUS] = { "hstatus", hmode, read_hstatus,
> > write_hstatus,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_HEDELEG] = { "hedeleg", hmode, read_hedeleg,
> > write_hedeleg,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_HIDELEG] = { "hideleg", hmode, NULL, NULL,
> > rmw_hideleg,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_HVIP] = { "hvip", hmode, NULL, NULL, rmw_hvip,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_HIE] = { "hie", hmode, NULL, NULL, rmw_hie,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren,
> > write_hcounteren,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_HGEIE] = { "hgeie", hmode, read_hgeie,
> > write_hgeie,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_HTVAL] = { "htval", hmode, read_htval,
> > write_htval,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_HTINST] = { "htinst", hmode, read_htinst,
> > write_htinst,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_HGEIP] = { "hgeip", hmode, read_hgeip,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_HGATP] = { "hgatp", hmode, read_hgatp,
> > write_hgatp,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta,
> > write_htimedelta,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah,
> > write_htimedeltah,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > +
> > + [CSR_VSSTATUS] = { "vsstatus", hmode, read_vsstatus,
> > write_vsstatus,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_VSIP] = { "vsip", hmode, NULL, NULL, rmw_vsip,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_VSIE] = { "vsie", hmode, NULL, NULL,
> > rmw_vsie ,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_VSTVEC] = { "vstvec", hmode, read_vstvec,
> > write_vstvec,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_VSSCRATCH] = { "vsscratch", hmode, read_vsscratch,
> > write_vsscratch,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_VSEPC] = { "vsepc", hmode, read_vsepc,
> > write_vsepc,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_VSCAUSE] = { "vscause", hmode, read_vscause,
> > write_vscause,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_VSTVAL] = { "vstval", hmode, read_vstval,
> > write_vstval,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_VSATP] = { "vsatp", hmode, read_vsatp,
> > write_vsatp,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > +
> > + [CSR_MTVAL2] = { "mtval2", hmode, read_mtval2,
> > write_mtval2,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> > + [CSR_MTINST] = { "mtinst", hmode, read_mtinst,
> > write_mtinst,
> > + .min_priv_ver =
> > PRIV_VERSION_1_12_0 },
> >
> > /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA)
> > */
> > [CSR_HVIEN] = { "hvien", aia_hmode, read_zero,
> > write_ignore },
> > @@ -3154,7 +3186,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > [CSR_VSIPH] = { "vsiph", aia_hmode32, NULL, NULL,
> > rmw_vsiph },
> >
> > /* Physical Memory Protection */
> > - [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg },
> > + [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg,
> > + .min_priv_ver = PRIV_VERSION_1_12_0 },
> > [CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
> > [CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
> > [CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
> > --
> > 2.30.2
> >
> >
>
--
Regards,
Atish
- [PATCH v3 0/6] Privilege version update, Atish Patra, 2022/02/06
- [PATCH v3 1/6] target/riscv: Define simpler privileged spec version numbering, Atish Patra, 2022/02/06
- [PATCH v3 2/6] target/riscv: Add the privileged spec version 1.12.0, Atish Patra, 2022/02/06
- [PATCH v3 3/6] target/riscv: Introduce privilege version field in the CSR ops., Atish Patra, 2022/02/06
- [PATCH v3 4/6] target/riscv: Add support for mconfigptr, Atish Patra, 2022/02/06
- [PATCH v3 5/6] target/riscv: Add *envcfg* CSRs support, Atish Patra, 2022/02/06
- [PATCH v3 6/6] target/riscv: Enable privileged spec version 1.12, Atish Patra, 2022/02/06