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[PATCH qemu v2 00/13] Add tail agnostic behavior for rvv instructions
From: |
~eopxd |
Subject: |
[PATCH qemu v2 00/13] Add tail agnostic behavior for rvv instructions |
Date: |
Wed, 23 Mar 2022 03:08:50 +0000 |
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s". An option
'rvv_ta_all_1s' is added to enable the behavior, it is default as
disabled.
There are multiple possibility for agnostic elements according to
v-spec. The main intent of this patch-set tries to add option that
can distinguish between tail policies. Setting agnostic elements to
all 1s makes things simple and allow QEMU to express this.
We may explore other possibility of agnostic behavior by adding
other options in the future. Please understand that this patch-set
is limited.
v2 updates:
- Addressed comments from Weiwei Li
- Added commit tail agnostic on load / store instructions (which
I forgot to include into the patch-set)
eopXD (13):
target/riscv: rvv: Rename ambiguous esz
target/riscv: rvv: Early exit when vstart >= vl
target/riscv: rvv: Add tail agnostic for vv instructions
target/riscv: rvv: Add tail agnostic for vector load / store
instructions
target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
target/riscv: rvv: Add tail agnostic for vector integer shift
instructions
target/riscv: rvv: Add tail agnostic for vector integer comparison
instructions
target/riscv: rvv: Add tail agnostic for vector integer merge and move
instructions
target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic
instructions
target/riscv: rvv: Add tail agnostic for vector floating-point
instructions
target/riscv: rvv: Add tail agnostic for vector reduction instructions
target/riscv: rvv: Add tail agnostic for vector mask instructions
target/riscv: rvv: Add tail agnostic for vector permutation
instructions
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 2 +
target/riscv/cpu_helper.c | 2 +
target/riscv/insn_trans/trans_rvv.c.inc | 66 +
target/riscv/internals.h | 5 +-
target/riscv/translate.c | 2 +
target/riscv/vector_helper.c | 1557 ++++++++++++++---------
7 files changed, 1020 insertions(+), 615 deletions(-)
--
2.34.1
- [PATCH qemu v2 00/13] Add tail agnostic behavior for rvv instructions,
~eopxd <=
- [PATCH qemu v2 01/13] target/riscv: rvv: Rename ambiguous esz, ~eopxd, 2022/03/22
- [PATCH qemu v2 02/13] target/riscv: rvv: Early exit when vstart >= vl, ~eopxd, 2022/03/22
- [PATCH qemu v2 04/13] target/riscv: rvv: Add tail agnostic for vector load / store instructions, ~eopxd, 2022/03/22
- [PATCH qemu v2 03/13] target/riscv: rvv: Add tail agnostic for vv instructions, ~eopxd, 2022/03/22
- [PATCH qemu v2 07/13] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, ~eopxd, 2022/03/22
- [PATCH qemu v2 06/13] target/riscv: rvv: Add tail agnostic for vector integer shift instructions, ~eopxd, 2022/03/22
- [PATCH qemu v2 11/13] target/riscv: rvv: Add tail agnostic for vector reduction instructions, ~eopxd, 2022/03/22
- [PATCH qemu v2 08/13] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions, ~eopxd, 2022/03/22
- [PATCH qemu v2 05/13] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, ~eopxd, 2022/03/22
- [PATCH qemu v2 12/13] target/riscv: rvv: Add tail agnostic for vector mask instructions, ~eopxd, 2022/03/22