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[PATCH qemu 5/9] target/riscv: rvv: Add mask agnostic for vector integer
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From: |
~eopxd |
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Subject: |
[PATCH qemu 5/9] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions |
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Date: |
Mon, 25 Apr 2022 14:18:47 -0000 |
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
target/riscv/vector_helper.c | 10 ++++++++++
2 files changed, 11 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index a085ef2c29..be08ec8a2e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1742,6 +1742,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 269e40c251..2b341d6679 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1401,12 +1401,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ if (vma) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
continue; \
} \
vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
@@ -1459,11 +1464,16 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
void *vs2, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ if (vma) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
continue; \
} \
vext_set_elem_mask(vd, i, \
--
2.34.2
- [PATCH qemu 0/9] Add mask agnostic behavior for rvv instructions, ~eopxd, 2022/04/25
- [PATCH qemu 3/9] target/riscv: rvv: Add mask agnostic for vx instructions, ~eopxd, 2022/04/25
- [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, ~eopxd, 2022/04/25
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, Weiwei Li, 2022/04/26
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, eop Chen, 2022/04/26
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, Weiwei Li, 2022/04/26
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, eop Chen, 2022/04/26
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, Weiwei Li, 2022/04/26
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, eop Chen, 2022/04/26
[PATCH qemu 5/9] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions,
~eopxd <=
[PATCH qemu 9/9] target/riscv: rvv: Add mask agnostic for vector permutation instructions, ~eopxd, 2022/04/25
[PATCH qemu 2/9] target/riscv: rvv: Add mask agnostic for vector load / store instructions, ~eopxd, 2022/04/25
[PATCH qemu 4/9] target/riscv: rvv: Add mask agnostic for vector integer shift instructions, ~eopxd, 2022/04/25
[PATCH qemu 8/9] target/riscv: rvv: Add mask agnostic for vector mask instructions, ~eopxd, 2022/04/25
[PATCH qemu 7/9] target/riscv: rvv: Add mask agnostic for vector floating-point instructions, ~eopxd, 2022/04/25
[PATCH qemu 6/9] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/04/25