[PATCH qemu 0/9] Add mask agnostic behavior for rvv instructions

[~eopxd]

According to v-spec, agnostic elements can be either kept as undisturbed
or set elements' bits to all 1s. To distinguish the difference of mask
policies, QEMU should be able to simulate the mask agnostic behavior as
"set masked-off elements' bits to all 1s". An option 'rvv_ma_all_1s' is
added to enable the behavior, it is default as disabled.

This patch set is based on the patch set "Add tail agnostic behavior for
rvv instructions".
Based on: <164863587444.17401.9965527486691250478-0@git.sr.ht>

Yueh-Ting (eop) Chen (9):
  target/riscv: rvv: Add mask agnostic for vv instructions
  target/riscv: rvv: Add mask agnostic for vector load / store
    instructions
  target/riscv: rvv: Add mask agnostic for vx instructions
  target/riscv: rvv: Add mask agnostic for vector integer shift
    instructions
  target/riscv: rvv: Add mask agnostic for vector integer comparison
    instructions
  target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic
    instructions
  target/riscv: rvv: Add mask agnostic for vector floating-point
    instructions
  target/riscv: rvv: Add mask agnostic for vector mask instructions
  target/riscv: rvv: Add mask agnostic for vector permutation
    instructions

 target/riscv/cpu.c                      |   1 +
 target/riscv/cpu.h                      |   2 +
 target/riscv/cpu_helper.c               |   2 +
 target/riscv/insn_trans/trans_rvv.c.inc |  32 +++++
 target/riscv/internals.h                |   5 +-
 target/riscv/translate.c                |   2 +
 target/riscv/vector_helper.c            | 159 ++++++++++++++++++++++--
 7 files changed, 189 insertions(+), 14 deletions(-)

-- 
2.34.2