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Re: [PATCH 1/5] target/riscv: Typo fix in sstc() predicate
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH 1/5] target/riscv: Typo fix in sstc() predicate |
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Date: |
Mon, 31 Oct 2022 10:40:51 +1000 |
On Fri, Oct 28, 2022 at 2:52 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> We should use "&&" instead of "&" when checking hcounteren.TM and
> henvcfg.STCE bits.
>
> Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 5c9a7ee287..716f9d960e 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -838,7 +838,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
> }
>
> if (riscv_cpu_virt_enabled(env)) {
> - if (!(get_field(env->hcounteren, COUNTEREN_TM) &
> + if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
> get_field(env->henvcfg, HENVCFG_STCE))) {
> return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> }
> --
> 2.34.1
>
>
- [PATCH 0/5] Nested virtualization fixes for QEMU, Anup Patel, 2022/10/27
- [PATCH 1/5] target/riscv: Typo fix in sstc() predicate, Anup Patel, 2022/10/27
- Re: [PATCH 1/5] target/riscv: Typo fix in sstc() predicate,
Alistair Francis <=
- [PATCH 4/5] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX, Anup Patel, 2022/10/27
- [PATCH 5/5] target/riscv: Ensure opcode is saved for all relevant instructions, Anup Patel, 2022/10/27
- [PATCH 2/5] target/riscv: Update VS timer whenever htimedelta changes, Anup Patel, 2022/10/27
- [PATCH 3/5] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP, Anup Patel, 2022/10/27