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Re: [PATCH 2/5] target/riscv: Update VS timer whenever htimedelta change
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH 2/5] target/riscv: Update VS timer whenever htimedelta changes |
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Date: |
Mon, 31 Oct 2022 10:42:36 +1000 |
On Fri, Oct 28, 2022 at 2:52 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> The htimedelta[h] CSR has impact on the VS timer comparison so we
> should call riscv_timer_write_timecmp() whenever htimedelta changes.
>
> Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 716f9d960e..4b1a608260 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -2722,6 +2722,8 @@ static RISCVException read_htimedelta(CPURISCVState
> *env, int csrno,
> static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> + RISCVCPU *cpu = env_archcpu(env);
> +
> if (!env->rdtime_fn) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
> @@ -2731,6 +2733,12 @@ static RISCVException write_htimedelta(CPURISCVState
> *env, int csrno,
> } else {
> env->htimedelta = val;
> }
> +
> + if (cpu->cfg.ext_sstc && env->rdtime_fn) {
> + riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
> + env->htimedelta, MIP_VSTIP);
> + }
> +
> return RISCV_EXCP_NONE;
> }
>
> @@ -2748,11 +2756,19 @@ static RISCVException read_htimedeltah(CPURISCVState
> *env, int csrno,
> static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> + RISCVCPU *cpu = env_archcpu(env);
> +
> if (!env->rdtime_fn) {
> return RISCV_EXCP_ILLEGAL_INST;
> }
>
> env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
> +
> + if (cpu->cfg.ext_sstc && env->rdtime_fn) {
> + riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
> + env->htimedelta, MIP_VSTIP);
> + }
> +
> return RISCV_EXCP_NONE;
> }
>
> --
> 2.34.1
>
>
- [PATCH 0/5] Nested virtualization fixes for QEMU, Anup Patel, 2022/10/27
- [PATCH 1/5] target/riscv: Typo fix in sstc() predicate, Anup Patel, 2022/10/27
- [PATCH 4/5] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX, Anup Patel, 2022/10/27
- [PATCH 5/5] target/riscv: Ensure opcode is saved for all relevant instructions, Anup Patel, 2022/10/27
- [PATCH 2/5] target/riscv: Update VS timer whenever htimedelta changes, Anup Patel, 2022/10/27
- Re: [PATCH 2/5] target/riscv: Update VS timer whenever htimedelta changes,
Alistair Francis <=
- [PATCH 3/5] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP, Anup Patel, 2022/10/27