[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH 14/15] hw/riscv: opentitan: Drop "hartid-base" and "priority-
|
From: |
Bin Meng |
|
Subject: |
Re: [PATCH 14/15] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization |
|
Date: |
Wed, 7 Dec 2022 18:11:23 +0800 |
Hi Alistair,
On Wed, Dec 7, 2022 at 12:38 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Fri, Dec 2, 2022 at 12:09 AM Bin Meng <bmeng@tinylab.org> wrote:
> >
> > "hartid-base" and "priority-base" are zero by default. There is no
> > need to initialize them to zero again.
>
> What is the defaults change though? I feel like these are worth leaving in
>
If the defaults change we should review all codes that use this model
and do necessary change accordingly. I just see no need to
re-initialize them to the default value, that's why we have a default
one assigned. But I am fine to keep these codes if you think it's
worth it.
Regards,
Bin
- [PATCH 10/15] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, (continued)
- [PATCH 10/15] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/01
- [PATCH 12/15] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb, Bin Meng, 2022/12/01
- [PATCH 13/15] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0, Bin Meng, 2022/12/01
- [PATCH 14/15] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization, Bin Meng, 2022/12/01
- [PATCH 15/15] hw/intc: sifive_plic: Fix the pending register range check, Bin Meng, 2022/12/01
- Re: [PATCH 15/15] hw/intc: sifive_plic: Fix the pending register range check, Alistair Francis, 2022/12/07
- Re: [PATCH 01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Alistair Francis, 2022/12/04