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Re: [PATCH 14/15] hw/riscv: opentitan: Drop "hartid-base" and "priority-
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH 14/15] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization |
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Date: |
Wed, 7 Dec 2022 14:37:34 +1000 |
On Fri, Dec 2, 2022 at 12:09 AM Bin Meng <bmeng@tinylab.org> wrote:
>
> "hartid-base" and "priority-base" are zero by default. There is no
> need to initialize them to zero again.
What is the defaults change though? I feel like these are worth leaving in
Alistair
>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
> hw/riscv/opentitan.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index be7ff1eea0..da73aa51f5 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -165,10 +165,8 @@ static void lowrisc_ibex_soc_realize(DeviceState
> *dev_soc, Error **errp)
>
> /* PLIC */
> qdev_prop_set_string(DEVICE(&s->plic), "hart-config", "M");
> - qdev_prop_set_uint32(DEVICE(&s->plic), "hartid-base", 0);
> qdev_prop_set_uint32(DEVICE(&s->plic), "num-sources", 180);
> qdev_prop_set_uint32(DEVICE(&s->plic), "num-priorities", 3);
> - qdev_prop_set_uint32(DEVICE(&s->plic), "priority-base", 0x00);
> qdev_prop_set_uint32(DEVICE(&s->plic), "pending-base", 0x1000);
> qdev_prop_set_uint32(DEVICE(&s->plic), "enable-base", 0x2000);
> qdev_prop_set_uint32(DEVICE(&s->plic), "enable-stride", 32);
> --
> 2.34.1
>
>
- Re: [PATCH 11/15] hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev", (continued)
- [PATCH 10/15] hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC, Bin Meng, 2022/12/01
- [PATCH 12/15] hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb, Bin Meng, 2022/12/01
- [PATCH 13/15] hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0, Bin Meng, 2022/12/01
- [PATCH 14/15] hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization, Bin Meng, 2022/12/01
- [PATCH 15/15] hw/intc: sifive_plic: Fix the pending register range check, Bin Meng, 2022/12/01
- Re: [PATCH 15/15] hw/intc: sifive_plic: Fix the pending register range check, Alistair Francis, 2022/12/07
- Re: [PATCH 01/15] hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC, Alistair Francis, 2022/12/04