[PATCH 0/5] target/riscv: Fix pointer mask related support

[Weiwei Li]

This patchset tries to fix some problems in current implementation for pointer
mask extension, and add support for pointer mask of instruction fetch.

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-pm-fix

Weiwei Li (5):
  target/riscv: Fix effective address for pointer mask
  target/riscv: Use sign-extended data address when xl = 32
  target/riscv: Fix pointer mask transformation for vector address
  target/riscv: take xl into consideration for vector address
  target/riscv: Add pointer mask support for instruction fetch

 target/riscv/cpu.h           |  1 +
 target/riscv/cpu_helper.c    | 25 +++++++++++++++++++++++--
 target/riscv/csr.c           |  2 --
 target/riscv/translate.c     | 16 ++++++++++++----
 target/riscv/vector_helper.c |  5 ++++-
 5 files changed, 40 insertions(+), 9 deletions(-)

-- 
2.25.1