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From: | liweiwei |
Subject: | Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch |
Date: | Tue, 28 Mar 2023 11:14:27 +0800 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 |
On 2023/3/28 9:55, liweiwei wrote:
I don't understand.
On 2023/3/28 02:04, Richard Henderson wrote:
On 3/27/23 03:00, Weiwei Li wrote:
@@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
+ if (access_type == MMU_INST_FETCH) {
+ address = adjust_pc_address(env, address);
+ }
Why do you want to do this so late, as opposed to earlier in cpu_get_tb_cpu_state?
In this way, the pc for tb may be different from the reg pc.
Then the pc register will be wrong if sync from tb.
I think you should give an explain here why it is wrong.
Zhiwei
Assume the pc is 0x1fff 0000, pmmask is 0xf000 0000, if we adjust pc in cpu_get_tb_cpu_state,
then the tb->pc will be 0x0fff 0000.
If we sync pc from tb by riscv_cpu_synchronize_from_tb()
Then the pc will be updated to 0x0fff 0000 in this case, which will different from the original value.
I ignore many internal steps in above case. Any critical condition I missed? or any misunderstood?
Regards,
Weiwei Li
Regards,
Weiwei Li
r~
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