Re: [PATCH 5/5] target/riscv: Add pointer mask support for instruction fetch

[liweiwei]

On 2023/3/28 11:31, Richard Henderson wrote:
> On 3/27/23 18:55, liweiwei wrote:
> > On 2023/3/28 02:04, Richard Henderson wrote:
> > > On 3/27/23 03:00, Weiwei Li wrote:
> > > > @@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr 
> > > > address, int size,
> > > >       qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d 
> > > > mmu_idx %d\n",
> > > >                     __func__, address, access_type, mmu_idx);
> > > >   +    if (access_type == MMU_INST_FETCH) {
> > > > +        address = adjust_pc_address(env, address);
> > > > +    }
> > >
> > > Why do you want to do this so late, as opposed to earlier in 
> > > cpu_get_tb_cpu_state?
> >
> > In this way, the pc for tb may be different from the reg pc. Then the 
> > pc register will be wrong if sync from tb.
>
> Hmm, true.
>
> But you certainly cannot adjust the address in tlb_fill, as you'll be 
> producing different result for read/write and exec.  You could 
> plausibly use a separate mmu_idx, but that's not ideal either.
>
> The best solution might be to implement pc-relative translation 
> (CF_PCREL).  At which point cpu_pc always has the correct results and 
> we make relative adjustments to that.

I'm not very familiar with how CF_PCREL works currently. I'll try this 
way later.

Regards,

Weiwei Li

> r~