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Re: [avr-chat] Missed Optimisation ?

From: bob
Subject: Re: [avr-chat] Missed Optimisation ?
Date: Tue, 01 Mar 2011 16:13:17 +0100
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On 01/03/11 15:58, Graham Davies wrote:
> bob wrote:
>> by this logic the missing 'OR' instructions could also affect external
>> hardware as they are read-modify-write, but these are optimised away.
> No, no, no.  The entire statement is read-modify-write.  Read 32-bits,
> modify 32-bits and write back 32-bits.  Once you've got the 32-bits, if
> you know that only one byte will ever change, there is no need to fiddle
> with the others.  Just write them back as they were.  To break this up
> into multiple read-modify-writes would be totally in violation of the
> use of the volatile storage qualifier.
> Graham.
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> AVR-chat mailing list
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Misunderstanding Graham,
I didn't mean to imply 4 read-OR-write cycles, just that with an unknown
hardware (OK, this is AVR and the OR is to registers in the CPU, but
other configurations are possible) the OR itself (which is a
read-modify-write operation) could have side effects.
Anyway thanks for all the discussion.
I think Erik is right, in ISRs either inspect the compiler code very
carefully or write in assembler yourself.


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