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Re: [avr-chat] Missed Optimisation ?

From: Graham Davies
Subject: Re: [avr-chat] Missed Optimisation ?
Date: Tue, 01 Mar 2011 20:24:28 -0500

Michael Hennebry wrote:

On further examination, I did find a "volatile uint32_t result;".
In context, I would guess that it was a complete
statement in the same file as the ISR.
Note the absence of attributes.
How could result not be in internal SRAM?

You may know that 'result' is going to be in internal SRAM, but you know things that the compiler doesn't. The compiler just puts the variable in memory.

The compiler doesn't know whether the programmer is nuts.

... and is not required to make the program behave sensibly when the programmer does something nutty like calling an ISR as an ordinary function.

That is not the same as blinding it to
things it can see in the source code.

The compiler is not allowed to infer that just because a variable is only accessed from one place in the source code it can see, that it is not also accessed from source code it cannot see during the translation.

Can you give an example that cannot be
eliminated by looking at the source code?

No, but that's not the point. The compiler can't see all the source code of the project at the same time. If a variable is accessed by two different threads of execution that appear in two different translation units, the compiler cannot know that it must avoid certain optimizations unless the programmer "tells it" using the volatile storage qualifier.

PORTB |= _BV(3);
is usually compiled as an SBI instruction.
Following the volatile rules blindly
would require at least two accesses.

Strictly speaking, this AVR-specific optimization violates the language specification, given that PORTB is volatile. The compiler should generate code that reads the PORTB register, performs the OR operation and then writes the result back to the PORTB register. Actually, I would hazard a guess that this is what the compiler actually does and it is some post-compilation step that embodies specific knowledge about the AVR architecture that swaps out the read-modify-write for the set-bit-immediate.


P.S. We may be descending into a personal argument. I would be happy at this point to say "we're both right, from out different points of view, but are perhaps not explaining it well to each other". OK?

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