[A bit longer one] Newbie finds himself confused by...

[Filip Miletic]

Dear friends,

This is my first post to this list and it has been a few days that I had
the opportunity of examining electric. I am advancing through your archive
and the docs but have a few problems that seem to have passed unmentioned here.
Please bear with me as there might be questions I ask that are faq by now and
which I missed on the first archive read.

<intro>
First for the introduction. I am an EE student that needs to make a flip-flop
layout for his semester coursework. You might find this a too easy task but
please
bear in mind that I live in a country simply too far away from contemporary
VLSI. The technology is 2u CMOS from MOSIS (as far as I understood, this should 
be the same) and the recommended tool is an ancient DOS ledit demo version from 
tanner.com. This package is very annoying for several reasons including its 
inability to expand beyond 640K, lack of export options, poor screen resolution,
non-existent documentation and extraction features. This is why I turned
to electric, hoping to find a full feature tool with source code, docs and 
good advice available. 

I would also like to try to persuade my professor to switch to electric for all
the benefits it offers to students (first of which, by act of force majeure, is
it being free).

System configuration is Mandrake 8.0 w/2.4.x kernel, Xfree86 4.0.x, P1 @ 233.
</intro>

I have several questions:

1. I built electric with Xaw, since I cannot afford motif :) and dislike it in
general. I have noticed that redrawing windows takes quite some time, which is
in particular noticeable when resizing or moving an electric window which
partially 
occludes another one. Dialogs which appear on top of a facet can disappear if
an user tries to resize the underlying window. Actually, the widgets are all
there
as you can move them around but are invisible. Some dialog text boxes tend to
stay 
on top of the desktop after the dialog has gone away etc. Is there a way 
I could work around this, besides having only one window at the desktop at all
times?

2. I (am expected to) use 2u cmos technology. How does the ledit morbn20 relate
to
this one?

3. I compared the work of a colleague of mine that was done in ledit (the
horrific 
edition) [http://tesla.rcub.bg.ac.yu/~filmil/xfiles/layout.gif] 
with a quick few-invertors layout in electric. It seems that, for instance,
ledit allows narrower distance between the transistor active area and metal-diff
contact
than electric, thus making smaller transistors. Are the design rules for
morbn20(ledit) 
and cmos(electric) compatible?  This is an important question as I am required
to 
have no design rule errors in ledit and still maintain the surface to a minimum.

4. There is a problem with the transistor node (i.e. nmos) in electric's cmos
technology.
Namely, drawing it and pulling out a polysilicon arc out of it generates a DRC
violation
stating this polysilicon is too close to transistor's PP layer. I have
discovered a rule
which states min distance between unconnected poly and PP, which seems to have
been
employed here. However, I see no way I could then connect the transistor gate to
anything
as this positively requires an arc from any of its terminals.

The same holds for making a diffusion arc away from the transistor. 
This does not happen with transistor_well(pmos) node,
as well as with mocmos' p and nmos. If indeed this is a bug, could anyone point
out 
how I could correct it. Technology edit hints are ok. C edit hints are also
acceptable,
but I would probably refrain from tracing the error in the source as that would
lead
me off my coursework mainstream at the moment when time is a precious resource.

TIA,
f.

--
Filip Miletic  EE->uE student, ETF BG FRY http://www.etf.bg.ac.yu
mailto:filmil*galeb-etf-bg-ac-yu http://galeb.etf.bg.ac.yu/~filmil
Linux Users Group YU (LUGY) http://www.linux.org.yu