Re: [A bit longer one] Newbie finds himself confused by...

[Steven Rubin]

This message did not make it to the list the first time...

> 1. I built electric with Xaw, since I cannot afford motif :) and dislike it in
> general. I have noticed that redrawing windows takes quite some time, which is
> in particular noticeable when resizing or moving an electric window which 
> partially
> occludes another one. Dialogs which appear on top of a facet can disappear if
> an user tries to resize the underlying window. Actually, the widgets are 
> all there
> as you can move them around but are invisible. Some dialog text boxes tend 
> to stay
> on top of the desktop after the dialog has gone away etc. Is there a way
> I could work around this, besides having only one window at the desktop at all
> times?

The "aw" (Athena Widgets) are old and not well supported.  You can get 
LessTif for free and you can also get "Open Motif" for free, so you need 
not pay for a better interface.

> 2. I (am expected to) use 2u cmos technology. How does the ledit morbn20 
> relate
> to this one?

I am not familiar with "ledit" technologies.  You should be able to switch 
the "mocmos" technology to "scmos" rules (as opposed to "submicron" or 
"deep") and set lambda appropriately, and it will be acceptable to MOSIS.

> 3. I compared the work of a colleague of mine that was done in ledit (the 
> horrific
> edition) [http://tesla.rcub.bg.ac.yu/~filmil/xfiles/layout.gif]
> with a quick few-invertors layout in electric. It seems that, for instance,
> ledit allows narrower distance between the transistor active area and 
> metal-diff contact
> than electric, thus making smaller transistors. Are the design rules for 
> morbn20(ledit)
> and cmos(electric) compatible?  This is an important question as I am 
> required to
> have no design rule errors in ledit and still maintain the surface to a 
> minimum.

Rather than compare "ledit" and "electric", why not look at the actual 
MOSIS rules, published on their web page (www.mosis.org)?  Then you will 
know whose rules are correct.

> 4. There is a problem with the transistor node (i.e. nmos) in electric's 
> cmos technology.
> Namely, drawing it and pulling out a polysilicon arc out of it generates a 
> DRC violation
> stating this polysilicon is too close to transistor's PP layer. I have 
> discovered a rule
> which states min distance between unconnected poly and PP, which seems to 
> have been
> employed here. However, I see no way I could then connect the transistor 
> gate to anything
> as this positively requires an arc from any of its terminals.
>
> The same holds for making a diffusion arc away from the transistor.
> This does not happen with transistor_well(pmos) node,
> as well as with mocmos' p and nmos. If indeed this is a bug, could anyone 
> point out
> how I could correct it. Technology edit hints are ok. C edit hints are 
> also acceptable,
> but I would probably refrain from tracing the error in the source as that 
> would lead
> me off my coursework mainstream at the moment when time is a precious 
> resource.

I am not aware of this problem.  If you can place a single transistor, wire 
it up, and get a design rule violation, then this is a bug that I want to 
see.  You can send a small library to me that exhibits this bug and I will 
look at it.

   -Steven Rubin