Re: [Discuss-gnuradio] Re: tx_chain - Verilog question

[Brian Padalino]

On Nov 30, 2007 6:29 PM, Ronald Jetli <address@hidden> wrote:
> Thank you Brian !
>
>  I am posting the test bench I am using to simulate / test tx_chain buffer.
> I think it has
>  been set up properly to simulate CIC. And I do follow the steps while
> stimulating.
>
>  However, I am having trouble setting up test cases for phase accumulator /
> Cordic.
>
>  I am posting the code below. It should'nt take much change (atmost few
> lines), but I am stuck with this one.It just dosent seem to work
>  for Cordic / Phase accumulator.
>
>  Can anyone please chip in ?
>
>  The Cordic test bench in fpga folder wasen't good either. It needs
> "sine.txt" file, which is missing.

You need to assert the interpolator_strobe and sample_strobe on a
consistent frequency basis - eg: once every 15 clock cycles.  You
can't just randomly assert and deassert them.

You have no frequency set.  I believe this frequency should be the
phase difference between samples of the CORDIC for each sample that
goes in where 2^31-1 is equal to 2*PI.

You probably want to see a sine wave or some filtered signal - try a
pulse train, {1, 0, 1, 0, ...} or you can download a math_real.v
module I wrote from here:

    
http://www.gnuradio.org/trac/browser/gnuradio/branches/developers/zhuochen/simulations/burst_test/math_real.v

Brian