Re: [lwip-users] Recv UDP Problem

[Michael Steinberg]

What do you mean by cache memory? The point of DMA transfers is 
bypassing the cpu altogether, and since the i&d caches are part of the 
cpu, they don't witness any memory reads&writes the DMA transfers 
initiate. One could potentially transfer that information to the caches 
from the memory bus matrix hubs, but at least STM32F7 does not do so, 
which leaves multiple options.

- clear&invalidate the caches manually on reads/writes to memory shared 
with dma operations
- somehow mark those regions as uncached if the mpu supports that
- use core coupled memory which is always uncached iff the dma engines 
can write to it
- disable d-cache altogether (ugh!)

Michael


Am 25.11.2016 um 21:41 schrieb Mike Fleetwood:
> Hi,
>
> I'm just starting the same process - migrating from m4 to m7 
> (eventually h7).
>
> Surely the cache memory gets invalidated automatically regardless of 
> the source of writing to it?
>
> Many thanks,
>
> Mike (a different one!).
>
>
> On 25/11/2016 16:35, Michael Steinberg wrote:
> > Hi,
> >
> > You were reporting the same software works on m4 but fails to work 
> > reliably on m7. The most prominent difference that can cause issues 
> > between m4 and m7 is that the latter has data caches, where the 
> > former has none. Possible situation: The dma writes a frame to cached 
> > memory, the mcu data cache is not invalidated, interrupt is raised, 
> > the isr which polls the dma descriptor chain reads from memory but 
> > gets a cache hit and reads outdated data.
> >
> > Michael
> >
> >
> > Am 25.11.2016 um 14:34 schrieb mgirke:
> > > @Michael: What exactly do you mean?
> > >
> > > no so far I am using two netconns, one for each task. but good to know
> > > 2.0.0. offers that.
> > >
> > > thanks!
> > >
> > >
> > >
> > > --
> > > View this message in context: 
> > > http://lwip.100.n7.nabble.com/Recv-UDP-Problem-tp27826p27900.html
> > > Sent from the lwip-users mailing list archive at Nabble.com.
> > >
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