[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 052/118] spapr_pci: fix MSI limit
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 052/118] spapr_pci: fix MSI limit |
Date: |
Wed, 4 Jun 2014 14:43:53 +0200 |
From: Alexey Kardashevskiy <address@hidden>
At the moment XICS does not support interrupts reuse so sPAPR PHB
implements this. sPAPRPHBState holds array of 32 spapr_pci_msi to
describe PCI config address, first MSI and number of MSIs. Once
allocated for a device, QEMU tries reusing this config until the number
of MSIs changes.
Existing SPAPR guests call ibm,change-msi in a loop until the handler
returns the requested number of vectors.
Recently introduced check for the maximum number of MSI/MSIX vectors
supported by a device only works for a device which is new for PHB's
MSI cache. If it is already there, the check is not performed which
leads to new IRQ block allocation. This happens during PCI hotplug
even when the user hot plug the same device which he just hot unplugged.
This moves the check earlier.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
hw/ppc/spapr_pci.c | 34 ++++++++++++++++++----------------
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index c052917..1db73f2 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -280,7 +280,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */
unsigned int seq_num = rtas_ld(args, 5);
unsigned int ret_intr_type;
- int ndev, irq;
+ int ndev, irq, max_irqs = 0;
sPAPRPHBState *phb = NULL;
PCIDevice *pdev = NULL;
@@ -333,6 +333,23 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
}
trace_spapr_pci_msi("Configuring MSI", ndev, config_addr);
+ /* Check if the device supports as many IRQs as requested */
+ if (ret_intr_type == RTAS_TYPE_MSI) {
+ max_irqs = msi_nr_vectors_allocated(pdev);
+ } else if (ret_intr_type == RTAS_TYPE_MSIX) {
+ max_irqs = pdev->msix_entries_nr;
+ }
+ if (!max_irqs) {
+ error_report("Requested interrupt type %d is not enabled for
device#%d",
+ ret_intr_type, ndev);
+ rtas_st(rets, 0, -1); /* Hardware error */
+ return;
+ }
+ /* Correct the number if the guest asked for too many */
+ if (req_num > max_irqs) {
+ req_num = max_irqs;
+ }
+
/* Check if there is an old config and MSI number has not changed */
if (phb->msi_table[ndev].nvec && (req_num != phb->msi_table[ndev].nvec)) {
/* Unexpected behaviour */
@@ -343,21 +360,6 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu,
sPAPREnvironment *spapr,
/* There is no cached config, allocate MSIs */
if (!phb->msi_table[ndev].nvec) {
- int max_irqs = 0;
- if (ret_intr_type == RTAS_TYPE_MSI) {
- max_irqs = msi_nr_vectors_allocated(pdev);
- } else if (ret_intr_type == RTAS_TYPE_MSIX) {
- max_irqs = pdev->msix_entries_nr;
- }
- if (!max_irqs) {
- error_report("Requested interrupt type %d is not enabled for
device#%d",
- ret_intr_type, ndev);
- rtas_st(rets, 0, -1); /* Hardware error */
- return;
- }
- if (req_num > max_irqs) {
- req_num = max_irqs;
- }
irq = spapr_allocate_irq_block(req_num, false,
ret_intr_type == RTAS_TYPE_MSI);
if (irq < 0) {
--
1.8.1.4
- [Qemu-devel] [PULL 040/118] target-ppc: Introduce DFP Quantize, (continued)
- [Qemu-devel] [PULL 040/118] target-ppc: Introduce DFP Quantize, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 042/118] target-ppc: Introduce DFP Round to Integer, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 041/118] target-ppc: Introduce DFP Reround, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 034/118] target-ppc: Introduce DFP Divide, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 044/118] target-ppc: Introduce Round to DFP Short/Long, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 046/118] target-ppc: Introduce DFP Convert to Fixed, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 054/118] util: Add AES ShiftRows and InvShiftRows Tables, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 047/118] target-ppc: Introduce DFP Decode DPD to BCD, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 048/118] target-ppc: Introduce DFP Encode BCD to DPD, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 050/118] target-ppc: Introduce DFP Insert Biased Exponent, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 052/118] spapr_pci: fix MSI limit,
Alexander Graf <=
- [Qemu-devel] [PULL 053/118] util: Add S-Box and InvS-Box Arrays to Common AES Utils, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 059/118] KVM: PPC: Don't secretly add 1T segment feature to CPU, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 049/118] target-ppc: Introduce DFP Extract Biased Exponent, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 062/118] PPC: Fix TCG chunks that don't free their temps, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 057/118] target-arm: Use Common Tables in AES Instructions, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 056/118] target-i386: Use Common ShiftRows and InvShiftRows Tables, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 063/118] PPC: Fail on leaking temporaries, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 065/118] PPC: Add definitions for GIVORs, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 051/118] target-ppc: Introduce DFP Shift Significand, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 060/118] PPC: e500: some pci related cleanup, Alexander Graf, 2014/06/04