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[Qemu-devel] [PULL 056/118] target-i386: Use Common ShiftRows and InvShi
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 056/118] target-i386: Use Common ShiftRows and InvShiftRows Tables |
Date: |
Wed, 4 Jun 2014 14:43:57 +0200 |
From: Tom Musta <address@hidden>
This patch eliminates the (now) redundant copy of the Advanced Encryption
Standard (AES)
ShiftRows and InvShiftRows tables; the code is updated to use the common tables
declared in
include/qemu/aes.h.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-i386/ops_sse.h | 32 +++++++++++++-------------------
1 file changed, 13 insertions(+), 19 deletions(-)
diff --git a/target-i386/ops_sse.h b/target-i386/ops_sse.h
index eb24b5f..886e0a8 100644
--- a/target-i386/ops_sse.h
+++ b/target-i386/ops_sse.h
@@ -17,6 +17,9 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+
+#include "qemu/aes.h"
+
#if SHIFT == 0
#define Reg MMXReg
#define XMM_ONLY(...)
@@ -2204,15 +2207,6 @@ void glue(helper_pclmulqdq, SUFFIX)(CPUX86State *env,
Reg *d, Reg *s,
d->Q(1) = resh;
}
-/* AES-NI op helpers */
-static const uint8_t aes_shifts[16] = {
- 0, 5, 10, 15, 4, 9, 14, 3, 8, 13, 2, 7, 12, 1, 6, 11
-};
-
-static const uint8_t aes_ishifts[16] = {
- 0, 13, 10, 7, 4, 1, 14, 11, 8, 5, 2, 15, 12, 9, 6, 3
-};
-
void glue(helper_aesdec, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
{
int i;
@@ -2220,10 +2214,10 @@ void glue(helper_aesdec, SUFFIX)(CPUX86State *env, Reg
*d, Reg *s)
Reg rk = *s;
for (i = 0 ; i < 4 ; i++) {
- d->L(i) = rk.L(i) ^ bswap32(AES_Td0[st.B(aes_ishifts[4*i+0])] ^
- AES_Td1[st.B(aes_ishifts[4*i+1])] ^
- AES_Td2[st.B(aes_ishifts[4*i+2])] ^
- AES_Td3[st.B(aes_ishifts[4*i+3])]);
+ d->L(i) = rk.L(i) ^ bswap32(AES_Td0[st.B(AES_ishifts[4*i+0])] ^
+ AES_Td1[st.B(AES_ishifts[4*i+1])] ^
+ AES_Td2[st.B(AES_ishifts[4*i+2])] ^
+ AES_Td3[st.B(AES_ishifts[4*i+3])]);
}
}
@@ -2234,7 +2228,7 @@ void glue(helper_aesdeclast, SUFFIX)(CPUX86State *env,
Reg *d, Reg *s)
Reg rk = *s;
for (i = 0; i < 16; i++) {
- d->B(i) = rk.B(i) ^ (AES_Td4[st.B(aes_ishifts[i])] & 0xff);
+ d->B(i) = rk.B(i) ^ (AES_Td4[st.B(AES_ishifts[i])] & 0xff);
}
}
@@ -2245,10 +2239,10 @@ void glue(helper_aesenc, SUFFIX)(CPUX86State *env, Reg
*d, Reg *s)
Reg rk = *s;
for (i = 0 ; i < 4 ; i++) {
- d->L(i) = rk.L(i) ^ bswap32(AES_Te0[st.B(aes_shifts[4*i+0])] ^
- AES_Te1[st.B(aes_shifts[4*i+1])] ^
- AES_Te2[st.B(aes_shifts[4*i+2])] ^
- AES_Te3[st.B(aes_shifts[4*i+3])]);
+ d->L(i) = rk.L(i) ^ bswap32(AES_Te0[st.B(AES_shifts[4*i+0])] ^
+ AES_Te1[st.B(AES_shifts[4*i+1])] ^
+ AES_Te2[st.B(AES_shifts[4*i+2])] ^
+ AES_Te3[st.B(AES_shifts[4*i+3])]);
}
}
@@ -2259,7 +2253,7 @@ void glue(helper_aesenclast, SUFFIX)(CPUX86State *env,
Reg *d, Reg *s)
Reg rk = *s;
for (i = 0; i < 16; i++) {
- d->B(i) = rk.B(i) ^ (AES_Te4[st.B(aes_shifts[i])] & 0xff);
+ d->B(i) = rk.B(i) ^ (AES_Te4[st.B(AES_shifts[i])] & 0xff);
}
}
--
1.8.1.4
- [Qemu-devel] [PULL 054/118] util: Add AES ShiftRows and InvShiftRows Tables, (continued)
- [Qemu-devel] [PULL 054/118] util: Add AES ShiftRows and InvShiftRows Tables, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 047/118] target-ppc: Introduce DFP Decode DPD to BCD, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 048/118] target-ppc: Introduce DFP Encode BCD to DPD, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 050/118] target-ppc: Introduce DFP Insert Biased Exponent, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 052/118] spapr_pci: fix MSI limit, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 053/118] util: Add S-Box and InvS-Box Arrays to Common AES Utils, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 059/118] KVM: PPC: Don't secretly add 1T segment feature to CPU, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 049/118] target-ppc: Introduce DFP Extract Biased Exponent, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 062/118] PPC: Fix TCG chunks that don't free their temps, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 057/118] target-arm: Use Common Tables in AES Instructions, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 056/118] target-i386: Use Common ShiftRows and InvShiftRows Tables,
Alexander Graf <=
- [Qemu-devel] [PULL 063/118] PPC: Fail on leaking temporaries, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 065/118] PPC: Add definitions for GIVORs, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 051/118] target-ppc: Introduce DFP Shift Significand, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 060/118] PPC: e500: some pci related cleanup, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 055/118] util: Add InvMixColumns, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 067/118] PPC: Add L1CFG1 SPR emulation, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 058/118] target-ppc: Refactor AES Instructions, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 064/118] PPC: Make all e500 CPUs SVR aware, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Alexander Graf, 2014/06/04