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[Qemu-devel] [PULL 062/118] PPC: Fix TCG chunks that don't free their te
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 062/118] PPC: Fix TCG chunks that don't free their temps |
Date: |
Wed, 4 Jun 2014 14:44:03 +0200 |
We want to make sure that every instruction cleans up after itself and
clears every temporary it allocated.
While checking whether this is already the case, I came across a few
cases where it isn't. This patch fixes every translation I found that
doesn't free their allocated temporaries.
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/translate.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 90d5999..e609d4e 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1223,6 +1223,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx,
TCGv ret, TCGv arg1,
}
tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
tcg_gen_add_tl(t0, t0, inv1);
+ tcg_temp_free(inv1);
tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
tcg_temp_free(t1);
tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
@@ -3919,6 +3920,9 @@ static inline void gen_bcond(DisasContext *ctx, int type)
gen_update_nip(ctx, ctx->nip);
tcg_gen_exit_tb(0);
}
+ if (type == BCOND_LR || type == BCOND_CTR) {
+ tcg_temp_free(target);
+ }
}
static void gen_bc(DisasContext *ctx)
@@ -4366,6 +4370,7 @@ static void gen_mtmsr(DisasContext *ctx)
tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
#endif
gen_helper_store_msr(cpu_env, msr);
+ tcg_temp_free(msr);
/* Must stop the translation as machine state (may have) changed */
/* Note that mtmsr is not always defined as context-synchronizing */
gen_stop_exception(ctx);
@@ -6500,6 +6505,7 @@ static void gen_tlbsx_booke206(DisasContext *ctx)
tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
gen_helper_booke206_tlbsx(cpu_env, t0);
+ tcg_temp_free(t0);
#endif
}
@@ -6533,6 +6539,7 @@ static void gen_tlbivax_booke206(DisasContext *ctx)
gen_addr_reg_index(ctx, t0);
gen_helper_booke206_tlbivax(cpu_env, t0);
+ tcg_temp_free(t0);
#endif
}
--
1.8.1.4
- [Qemu-devel] [PULL 044/118] target-ppc: Introduce Round to DFP Short/Long, (continued)
- [Qemu-devel] [PULL 044/118] target-ppc: Introduce Round to DFP Short/Long, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 046/118] target-ppc: Introduce DFP Convert to Fixed, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 054/118] util: Add AES ShiftRows and InvShiftRows Tables, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 047/118] target-ppc: Introduce DFP Decode DPD to BCD, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 048/118] target-ppc: Introduce DFP Encode BCD to DPD, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 050/118] target-ppc: Introduce DFP Insert Biased Exponent, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 052/118] spapr_pci: fix MSI limit, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 053/118] util: Add S-Box and InvS-Box Arrays to Common AES Utils, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 059/118] KVM: PPC: Don't secretly add 1T segment feature to CPU, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 049/118] target-ppc: Introduce DFP Extract Biased Exponent, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 062/118] PPC: Fix TCG chunks that don't free their temps,
Alexander Graf <=
- [Qemu-devel] [PULL 057/118] target-arm: Use Common Tables in AES Instructions, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 056/118] target-i386: Use Common ShiftRows and InvShiftRows Tables, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 063/118] PPC: Fail on leaking temporaries, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 065/118] PPC: Add definitions for GIVORs, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 051/118] target-ppc: Introduce DFP Shift Significand, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 060/118] PPC: e500: some pci related cleanup, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 055/118] util: Add InvMixColumns, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 067/118] PPC: Add L1CFG1 SPR emulation, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 058/118] target-ppc: Refactor AES Instructions, Alexander Graf, 2014/06/04
- [Qemu-devel] [PULL 064/118] PPC: Make all e500 CPUs SVR aware, Alexander Graf, 2014/06/04