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Re: [PATCH 07/20] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp
From: |
Peter Maydell |
Subject: |
Re: [PATCH 07/20] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp |
Date: |
Mon, 24 Aug 2020 17:44:49 +0100 |
On Sat, 15 Aug 2020 at 02:31, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The gvec operation was added after the initial implementation
> of the SEL instruction and was missed in the conversion.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate-sve.c | 31 ++++++++-----------------------
> 1 file changed, 8 insertions(+), 23 deletions(-)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- Re: [PATCH 16/20] target/arm: Fix sve_zip_p vs odd vector lengths, (continued)
- [PATCH 01/20] qemu/int128: Add int128_lshift, Richard Henderson, 2020/08/15
- [PATCH 20/20] target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd, Richard Henderson, 2020/08/15
- [PATCH 13/20] target/arm: Tidy SVE tszimm shift formats, Richard Henderson, 2020/08/15
- [PATCH 09/20] target/arm: Merge helper_sve_clr_* and helper_sve_movz_*, Richard Henderson, 2020/08/15
- [PATCH 07/20] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp, Richard Henderson, 2020/08/15
- Re: [PATCH 07/20] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp,
Peter Maydell <=
- [PATCH 08/20] target/arm: Split out gen_gvec_ool_zzzp, Richard Henderson, 2020/08/15
- [PATCH 17/20] target/arm: Fix sve_punpk_p vs odd vector lengths, Richard Henderson, 2020/08/15
- [PATCH 19/20] target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd, Richard Henderson, 2020/08/15
- [PATCH 11/20] target/arm: Split out gen_gvec_ool_zzz, Richard Henderson, 2020/08/15
- [PATCH 04/20] target/arm: Rearrange {sve,fp}_check_access assert, Richard Henderson, 2020/08/15