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[PATCH 08/20] target/arm: Split out gen_gvec_ool_zzzp
From: |
Richard Henderson |
Subject: |
[PATCH 08/20] target/arm: Split out gen_gvec_ool_zzzp |
Date: |
Fri, 14 Aug 2020 18:31:33 -0700 |
Model after gen_gvec_fn_zzz et al.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-sve.c | 35 ++++++++++++++++-------------------
1 file changed, 16 insertions(+), 19 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index aa7ed070e3..535d086838 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -142,8 +142,19 @@ static int pred_gvec_reg_size(DisasContext *s)
return size_for_gvec(pred_full_reg_size(s));
}
-/* Invoke a vector expander on two Zregs. */
+/* Invoke an out-of-line helper on 3 Zregs and a predicate. */
+static void gen_gvec_ool_zzzp(DisasContext *s, gen_helper_gvec_4 *fn,
+ int rd, int rn, int rm, int pg, int data)
+{
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ pred_full_reg_offset(s, pg),
+ vsz, vsz, data, fn);
+}
+/* Invoke a vector expander on two Zregs. */
static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
int esz, int rd, int rn)
{
@@ -314,16 +325,11 @@ static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz
*a)
static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a, gen_helper_gvec_4
*fn)
{
- unsigned vsz = vec_full_reg_size(s);
if (fn == NULL) {
return false;
}
if (sve_access_check(s)) {
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),
- vec_full_reg_offset(s, a->rn),
- vec_full_reg_offset(s, a->rm),
- pred_full_reg_offset(s, a->pg),
- vsz, vsz, 0, fn);
+ gen_gvec_ool_zzzp(s, fn, a->rd, a->rn, a->rm, a->pg, 0);
}
return true;
}
@@ -337,12 +343,7 @@ static void do_sel_z(DisasContext *s, int rd, int rn, int
rm, int pg, int esz)
gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h,
gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d
};
- unsigned vsz = vec_full_reg_size(s);
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
- vec_full_reg_offset(s, rn),
- vec_full_reg_offset(s, rm),
- pred_full_reg_offset(s, pg),
- vsz, vsz, 0, fns[esz]);
+ gen_gvec_ool_zzzp(s, fns[esz], rd, rn, rm, pg, 0);
}
#define DO_ZPZZ(NAME, name) \
@@ -2704,12 +2705,8 @@ static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a)
static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
{
if (sve_access_check(s)) {
- unsigned vsz = vec_full_reg_size(s);
- tcg_gen_gvec_4_ool(vec_full_reg_offset(s, a->rd),
- vec_full_reg_offset(s, a->rn),
- vec_full_reg_offset(s, a->rm),
- pred_full_reg_offset(s, a->pg),
- vsz, vsz, a->esz, gen_helper_sve_splice);
+ gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
+ a->rd, a->rn, a->rm, a->pg, 0);
}
return true;
}
--
2.25.1
- [PATCH 01/20] qemu/int128: Add int128_lshift, (continued)
- [PATCH 01/20] qemu/int128: Add int128_lshift, Richard Henderson, 2020/08/15
- [PATCH 20/20] target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd, Richard Henderson, 2020/08/15
- [PATCH 13/20] target/arm: Tidy SVE tszimm shift formats, Richard Henderson, 2020/08/15
- [PATCH 09/20] target/arm: Merge helper_sve_clr_* and helper_sve_movz_*, Richard Henderson, 2020/08/15
- [PATCH 07/20] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp, Richard Henderson, 2020/08/15
- [PATCH 08/20] target/arm: Split out gen_gvec_ool_zzzp,
Richard Henderson <=
- [PATCH 17/20] target/arm: Fix sve_punpk_p vs odd vector lengths, Richard Henderson, 2020/08/15
- [PATCH 19/20] target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd, Richard Henderson, 2020/08/15
- [PATCH 11/20] target/arm: Split out gen_gvec_ool_zzz, Richard Henderson, 2020/08/15
- [PATCH 04/20] target/arm: Rearrange {sve,fp}_check_access assert, Richard Henderson, 2020/08/15