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[PULL 06/18] target/riscv: Allow setting a two-stage lookup in the virt
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From: |
Alistair Francis |
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Subject: |
[PULL 06/18] target/riscv: Allow setting a two-stage lookup in the virt status |
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Date: |
Tue, 25 Aug 2020 11:48:24 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com
Message-Id:
<08cdefb171b1bdb0c9e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 18 ++++++++++++++++++
3 files changed, 21 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a804a5d0ba..383808bf88 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -321,6 +321,8 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
+bool riscv_cpu_two_stage_lookup(CPURISCVState *env);
+void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8117e8b5a7..ba0a5b50ff 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -467,6 +467,7 @@
* page table fault.
*/
#define FORCE_HS_EXCEP 2
+#define HS_TWO_STAGE 4
/* RV32 satp CSR field masks */
#define SATP32_MODE 0x80000000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index fd1d373b6f..e5e0d80c32 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -220,6 +220,24 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool
enable)
env->virt = set_field(env->virt, FORCE_HS_EXCEP, enable);
}
+bool riscv_cpu_two_stage_lookup(CPURISCVState *env)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return false;
+ }
+
+ return get_field(env->virt, HS_TWO_STAGE);
+}
+
+void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable)
+{
+ if (!riscv_has_ext(env, RVH)) {
+ return;
+ }
+
+ env->virt = set_field(env->virt, HS_TWO_STAGE, enable);
+}
+
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts)
{
CPURISCVState *env = &cpu->env;
--
2.28.0
- [PULL 00/18] riscv-to-apply queue, Alistair Francis, 2020/08/25
- [PULL 01/18] hw/riscv: Allow creating multiple instances of CLINT, Alistair Francis, 2020/08/25
- [PULL 02/18] hw/riscv: Allow creating multiple instances of PLIC, Alistair Francis, 2020/08/25
- [PULL 03/18] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines, Alistair Francis, 2020/08/25
- [PULL 04/18] hw/riscv: spike: Allow creating multiple NUMA sockets, Alistair Francis, 2020/08/25
- [PULL 06/18] target/riscv: Allow setting a two-stage lookup in the virt status,
Alistair Francis <=
- [PULL 05/18] hw/riscv: virt: Allow creating multiple NUMA sockets, Alistair Francis, 2020/08/25
- [PULL 10/18] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/08/25
- [PULL 07/18] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/25
- [PULL 08/18] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/25
- [PULL 09/18] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/08/25
- [PULL 11/18] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/08/25
- [PULL 12/18] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/08/25
- [PULL 13/18] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/08/25
- [PULL 14/18] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/08/25
- [PULL 16/18] target/riscv: Support the v0.6 Hypervisor extension CRSs, Alistair Francis, 2020/08/25