[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 11/18] target/riscv: Fix the interrupt cause code
From: |
Alistair Francis |
Subject: |
[PULL 11/18] target/riscv: Fix the interrupt cause code |
Date: |
Tue, 25 Aug 2020 11:48:29 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com
Message-Id:
<85b7fdba8abd87adb83275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0b4ad4bf46..661e790fdc 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -916,14 +916,15 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
!force_hs_execp) {
+ /* Trap to VS mode */
/*
* See if we need to adjust cause. Yes if its VS mode interrupt
* no if hypervisor has delegated one of hs mode's interrupt
*/
if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
- cause == IRQ_VS_EXT)
+ cause == IRQ_VS_EXT) {
cause = cause - 1;
- /* Trap to VS mode */
+ }
env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
} else if (riscv_cpu_virt_enabled(env)) {
/* Trap into HS mode, from virt */
--
2.28.0
- [PULL 01/18] hw/riscv: Allow creating multiple instances of CLINT, (continued)
- [PULL 01/18] hw/riscv: Allow creating multiple instances of CLINT, Alistair Francis, 2020/08/25
- [PULL 02/18] hw/riscv: Allow creating multiple instances of PLIC, Alistair Francis, 2020/08/25
- [PULL 03/18] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines, Alistair Francis, 2020/08/25
- [PULL 04/18] hw/riscv: spike: Allow creating multiple NUMA sockets, Alistair Francis, 2020/08/25
- [PULL 06/18] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/08/25
- [PULL 05/18] hw/riscv: virt: Allow creating multiple NUMA sockets, Alistair Francis, 2020/08/25
- [PULL 10/18] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/08/25
- [PULL 07/18] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/25
- [PULL 08/18] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/25
- [PULL 09/18] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/08/25
- [PULL 11/18] target/riscv: Fix the interrupt cause code,
Alistair Francis <=
- [PULL 12/18] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/08/25
- [PULL 13/18] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/08/25
- [PULL 14/18] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/08/25
- [PULL 16/18] target/riscv: Support the v0.6 Hypervisor extension CRSs, Alistair Francis, 2020/08/25
- [PULL 15/18] target/riscv: Only support little endian guests, Alistair Francis, 2020/08/25
- [PULL 17/18] target/riscv: Return the exception from invalid CSR accesses, Alistair Francis, 2020/08/25
- [PULL 18/18] target/riscv: Support the Virtual Instruction fault, Alistair Francis, 2020/08/25
- Re: [PULL 00/18] riscv-to-apply queue, Peter Maydell, 2020/08/25