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[PULL 14/18] target/riscv: Only support a single VSXL length
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From: |
Alistair Francis |
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Subject: |
[PULL 14/18] target/riscv: Only support a single VSXL length |
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Date: |
Tue, 25 Aug 2020 11:48:32 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id:
f3f4fd2ec22a07cc1d750e96895d6813f131de4d.1597259519.git.alistair.francis@wdc.com
Message-Id:
<f3f4fd2ec22a07cc1d750e96895d6813f131de4d.1597259519.git.alistair.francis@wdc.com>
---
target/riscv/csr.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f9ac21d687..390ef781e4 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -836,12 +836,21 @@ static int write_satp(CPURISCVState *env, int csrno,
target_ulong val)
static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->hstatus;
+#ifdef TARGET_RISCV64
+ /* We only support 64-bit VSXL */
+ *val = set_field(*val, HSTATUS_VSXL, 2);
+#endif
return 0;
}
static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
{
env->hstatus = val;
+#ifdef TARGET_RISCV64
+ if (get_field(val, HSTATUS_VSXL) != 2) {
+ qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN
options.");
+ }
+#endif
return 0;
}
--
2.28.0
- [PULL 04/18] hw/riscv: spike: Allow creating multiple NUMA sockets, (continued)
- [PULL 04/18] hw/riscv: spike: Allow creating multiple NUMA sockets, Alistair Francis, 2020/08/25
- [PULL 06/18] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/08/25
- [PULL 05/18] hw/riscv: virt: Allow creating multiple NUMA sockets, Alistair Francis, 2020/08/25
- [PULL 10/18] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/08/25
- [PULL 07/18] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/25
- [PULL 08/18] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/08/25
- [PULL 09/18] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/08/25
- [PULL 11/18] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/08/25
- [PULL 12/18] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/08/25
- [PULL 13/18] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/08/25
- [PULL 14/18] target/riscv: Only support a single VSXL length,
Alistair Francis <=
- [PULL 16/18] target/riscv: Support the v0.6 Hypervisor extension CRSs, Alistair Francis, 2020/08/25
- [PULL 15/18] target/riscv: Only support little endian guests, Alistair Francis, 2020/08/25
- [PULL 17/18] target/riscv: Return the exception from invalid CSR accesses, Alistair Francis, 2020/08/25
- [PULL 18/18] target/riscv: Support the Virtual Instruction fault, Alistair Francis, 2020/08/25
- Re: [PULL 00/18] riscv-to-apply queue, Peter Maydell, 2020/08/25