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[PULL 07/36] target/arm: Convert Neon 3-same-fp size field to MO_* in de
From: |
Peter Maydell |
Subject: |
[PULL 07/36] target/arm: Convert Neon 3-same-fp size field to MO_* in decode |
Date: |
Mon, 14 Sep 2020 15:06:12 +0100 |
In the Neon instructions, some instruction formats have a 2-bit size
field which corresponds exactly to QEMU's MO_8/16/32/64. However the
floating-point insns in the 3-same group have a 1-bit size field
which is "0 for 32-bit float and 1 for 16-bit float". Currently we
pass these values directly through to trans_ functions, which means
that when reading a particular trans_ function you need to know if
that insn uses a 2-bit size or a 1-bit size.
Move the handling of the 1-bit size to the decodetree file, so that
all these insns consistently pass a size to the trans_ function which
is an MO_8/16/32/64 value.
In this commit we switch over the insns using the 3same_fp and
3same_fp_q0 formats.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200903133209.5141-2-peter.maydell@linaro.org
---
target/arm/neon-dp.decode | 15 ++++++++++-----
target/arm/translate-neon.c.inc | 16 +++++++++++-----
2 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index 1e9e8592917..ea2f0dfcf16 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -45,11 +45,16 @@
@3same_q0 .... ... . . . size:2 .... .... .... . 0 . . .... \
&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
-# For FP insns the high bit of 'size' is used as part of opcode decode
-@3same_fp .... ... . . . . size:1 .... .... .... . q:1 . . .... \
- &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
-@3same_fp_q0 .... ... . . . . size:1 .... .... .... . 0 . . .... \
- &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
+# For FP insns the high bit of 'size' is used as part of opcode decode,
+# and the 'size' bit is 0 for 32-bit float and 1 for 16-bit float.
+# This converts this encoding to the same MO_8/16/32/64 values that the
+# integer neon insns use.
+%3same_fp_size 20:1 !function=neon_3same_fp_size
+
+@3same_fp .... ... . . . . . .... .... .... . q:1 . . .... \
+ &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%3same_fp_size
+@3same_fp_q0 .... ... . . . . . .... .... .... . 0 . . .... \
+ &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0 size=%3same_fp_size
VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index 2d4926316a4..255c1cf8a2a 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -49,6 +49,12 @@ static inline int rsub_8(DisasContext *s, int x)
return 8 - x;
}
+static inline int neon_3same_fp_size(DisasContext *s, int x)
+{
+ /* Convert 0==fp32, 1==fp16 into a MO_* value */
+ return MO_32 - x;
+}
+
/* Include the generated Neon decoder */
#include "decode-neon-dp.c.inc"
#include "decode-neon-ls.c.inc"
@@ -1049,7 +1055,7 @@ DO_3SAME_VQDMULH(VQRDMULH, qrdmulh)
WRAP_FP_GVEC(gen_##INSN##_fp16_3s, FPST_STD_F16, HFUNC) \
static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
{ \
- if (a->size != 0) { \
+ if (a->size == MO_16) { \
if (!dc_isar_feature(aa32_fp16_arith, s)) { \
return false; \
} \
@@ -1088,7 +1094,7 @@ static bool trans_VMAXNM_fp_3s(DisasContext *s, arg_3same
*a)
return false;
}
- if (a->size != 0) {
+ if (a->size == MO_16) {
if (!dc_isar_feature(aa32_fp16_arith, s)) {
return false;
}
@@ -1103,7 +1109,7 @@ static bool trans_VMINNM_fp_3s(DisasContext *s, arg_3same
*a)
return false;
}
- if (a->size != 0) {
+ if (a->size == MO_16) {
if (!dc_isar_feature(aa32_fp16_arith, s)) {
return false;
}
@@ -1135,7 +1141,7 @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same
*a,
assert(a->q == 0); /* enforced by decode patterns */
- fpstatus = fpstatus_ptr(a->size != 0 ? FPST_STD_F16 : FPST_STD);
+ fpstatus = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
vfp_reg_offset(1, a->vn),
vfp_reg_offset(1, a->vm),
@@ -1152,7 +1158,7 @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same
*a,
#define DO_3S_FP_PAIR(INSN,FUNC) \
static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
{ \
- if (a->size != 0) { \
+ if (a->size == MO_16) { \
if (!dc_isar_feature(aa32_fp16_arith, s)) { \
return false; \
} \
--
2.20.1
- [PULL 00/36] target-arm queue, Peter Maydell, 2020/09/14
- [PULL 01/36] hw/misc/a9scu: Do not allow invalid CPU count, Peter Maydell, 2020/09/14
- [PULL 02/36] hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields, Peter Maydell, 2020/09/14
- [PULL 03/36] hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields, Peter Maydell, 2020/09/14
- [PULL 04/36] hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP), Peter Maydell, 2020/09/14
- [PULL 05/36] hw/timer/armv7m_systick: assert that board code set system_clock_scale, Peter Maydell, 2020/09/14
- [PULL 06/36] decodetree: Improve identifier matching, Peter Maydell, 2020/09/14
- [PULL 07/36] target/arm: Convert Neon 3-same-fp size field to MO_* in decode,
Peter Maydell <=
- [PULL 08/36] target/arm: Convert Neon VCVT fp size field to MO_* in decode, Peter Maydell, 2020/09/14
- [PULL 09/36] target/arm: Convert VCMLA, VCADD size field to MO_* in decode, Peter Maydell, 2020/09/14
- [PULL 11/36] target/arm: Remove no-longer-reachable 32-bit KVM code, Peter Maydell, 2020/09/14
- [PULL 10/36] target/arm: Remove KVM support for 32-bit Arm hosts, Peter Maydell, 2020/09/14
- [PULL 12/36] hw/arm/mps2: New board model mps2-an386, Peter Maydell, 2020/09/14
- [PULL 13/36] hw/arm/mps2: New board model mps2-an500, Peter Maydell, 2020/09/14
- [PULL 14/36] docs/system/arm/mps2.rst: Make board list consistent, Peter Maydell, 2020/09/14
- [PULL 15/36] Deprecate Unicore32 port, Peter Maydell, 2020/09/14
- [PULL 16/36] Deprecate lm32 port, Peter Maydell, 2020/09/14
- [PULL 17/36] target/arm: Count PMU events when MDCR.SPME is set, Peter Maydell, 2020/09/14