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[PULL 08/36] target/arm: Convert Neon VCVT fp size field to MO_* in deco
From: |
Peter Maydell |
Subject: |
[PULL 08/36] target/arm: Convert Neon VCVT fp size field to MO_* in decode |
Date: |
Mon, 14 Sep 2020 15:06:13 +0100 |
Convert the insns using the 2reg_vcvt and 2reg_vcvt_f16 formats
to pass the size through to the trans function as a MO_* value
rather than the '0==f32, 1==f16' used in the fp 3-same encodings.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200903133209.5141-3-peter.maydell@linaro.org
---
target/arm/neon-dp.decode | 3 +--
target/arm/translate-neon.c.inc | 4 ++--
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index ea2f0dfcf16..51aa0f08194 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -256,9 +256,8 @@ VMINNM_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 1
.... @3same_fp
@2reg_shll_b .... ... . . . 001 shift:3 .... .... 0 . . . .... \
&2reg_shift vm=%vm_dp vd=%vd_dp size=0 q=0
-# We use size=0 for fp32 and size=1 for fp16 to match the 3-same encodings.
@2reg_vcvt .... ... . . . 1 ..... .... .... . q:1 . . .... \
- &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i5
+ &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
@2reg_vcvt_f16 .... ... . . . 11 .... .... .... . q:1 . . .... \
&2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index 255c1cf8a2a..213c1c2174a 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -1626,7 +1626,7 @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
return false;
}
- if (a->size != 0) {
+ if (a->size == MO_16) {
if (!dc_isar_feature(aa32_fp16_arith, s)) {
return false;
}
@@ -1646,7 +1646,7 @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift *a,
return true;
}
- fpst = fpstatus_ptr(a->size ? FPST_STD_F16 : FPST_STD);
+ fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
tcg_gen_gvec_2_ptr(rd_ofs, rm_ofs, fpst, vec_size, vec_size, a->shift, fn);
tcg_temp_free_ptr(fpst);
return true;
--
2.20.1
- [PULL 00/36] target-arm queue, Peter Maydell, 2020/09/14
- [PULL 01/36] hw/misc/a9scu: Do not allow invalid CPU count, Peter Maydell, 2020/09/14
- [PULL 02/36] hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields, Peter Maydell, 2020/09/14
- [PULL 03/36] hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields, Peter Maydell, 2020/09/14
- [PULL 04/36] hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP), Peter Maydell, 2020/09/14
- [PULL 05/36] hw/timer/armv7m_systick: assert that board code set system_clock_scale, Peter Maydell, 2020/09/14
- [PULL 06/36] decodetree: Improve identifier matching, Peter Maydell, 2020/09/14
- [PULL 07/36] target/arm: Convert Neon 3-same-fp size field to MO_* in decode, Peter Maydell, 2020/09/14
- [PULL 08/36] target/arm: Convert Neon VCVT fp size field to MO_* in decode,
Peter Maydell <=
- [PULL 09/36] target/arm: Convert VCMLA, VCADD size field to MO_* in decode, Peter Maydell, 2020/09/14
- [PULL 11/36] target/arm: Remove no-longer-reachable 32-bit KVM code, Peter Maydell, 2020/09/14
- [PULL 10/36] target/arm: Remove KVM support for 32-bit Arm hosts, Peter Maydell, 2020/09/14
- [PULL 12/36] hw/arm/mps2: New board model mps2-an386, Peter Maydell, 2020/09/14
- [PULL 13/36] hw/arm/mps2: New board model mps2-an500, Peter Maydell, 2020/09/14
- [PULL 14/36] docs/system/arm/mps2.rst: Make board list consistent, Peter Maydell, 2020/09/14
- [PULL 15/36] Deprecate Unicore32 port, Peter Maydell, 2020/09/14
- [PULL 16/36] Deprecate lm32 port, Peter Maydell, 2020/09/14
- [PULL 17/36] target/arm: Count PMU events when MDCR.SPME is set, Peter Maydell, 2020/09/14
- [PULL 18/36] hw/arm: versal-virt: Correct the tx/rx GEM clocks, Peter Maydell, 2020/09/14