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[PATCH v3 17/17] hw/block/nvme: change controller pci id
From: |
Klaus Jensen |
Subject: |
[PATCH v3 17/17] hw/block/nvme: change controller pci id |
Date: |
Tue, 22 Sep 2020 10:45:33 +0200 |
From: Klaus Jensen <k.jensen@samsung.com>
There are two reasons for changing this:
1. The nvme device currently uses an internal Intel device id.
2. Since commits "nvme: fix write zeroes offset and count" and "nvme:
support multiple namespaces" the controller device no longer has
the quirks that the Linux kernel think it has.
As the quirks are applied based on pci vendor and device id, change
them to get rid of the quirks.
To keep backward compatibility, add a new 'use-intel-id' parameter to
the nvme device to force use of the Intel vendor and device id. This is
off by default but add a compat property to set this for 5.1 machines
and older. If a 5.1 machine is booted (or the use-intel-id parameter is
explicitly set to true), the Linux kernel will just apply these
unnecessary quirks:
1. NVME_QUIRK_IDENTIFY_CNS which says that the device does not support
anything else than values 0x0 and 0x1 for CNS (Identify Namespace
and Identify Namespace). With multiple namespace support, this just
means that the kernel will "scan" namespaces instead of using
"Active Namespace ID list" (CNS 0x2).
2. NVME_QUIRK_DISABLE_WRITE_ZEROES. The nvme device started out with a
broken Write Zeroes implementation which has since been fixed in
commit 9d6459d21a6e ("nvme: fix write zeroes offset and count").
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com>
---
hw/block/nvme.h | 1 +
hw/block/nvme.c | 12 ++++++++++--
hw/core/machine.c | 1 +
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/block/nvme.h b/hw/block/nvme.h
index d96ec15cdffb..e080a2318a50 100644
--- a/hw/block/nvme.h
+++ b/hw/block/nvme.h
@@ -15,6 +15,7 @@ typedef struct NvmeParams {
uint8_t aerl;
uint32_t aer_max_queued;
uint8_t mdts;
+ bool use_intel_id;
} NvmeParams;
typedef struct NvmeAsyncEvent {
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index d6749fdd96e1..da8344f196a8 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -2683,6 +2683,15 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice
*pci_dev, Error **errp)
pci_conf[PCI_INTERRUPT_PIN] = 1;
pci_config_set_prog_interface(pci_conf, 0x2);
+
+ if (n->params.use_intel_id) {
+ pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(pci_conf, 0x5845);
+ } else {
+ pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REDHAT);
+ pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REDHAT_NVME);
+ }
+
pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS);
pcie_endpoint_cap_init(pci_dev, 0x80);
@@ -2836,6 +2845,7 @@ static Property nvme_props[] = {
DEFINE_PROP_UINT8("aerl", NvmeCtrl, params.aerl, 3),
DEFINE_PROP_UINT32("aer_max_queued", NvmeCtrl, params.aer_max_queued, 64),
DEFINE_PROP_UINT8("mdts", NvmeCtrl, params.mdts, 7),
+ DEFINE_PROP_BOOL("use-intel-id", NvmeCtrl, params.use_intel_id, false),
DEFINE_PROP_END_OF_LIST(),
};
@@ -2852,8 +2862,6 @@ static void nvme_class_init(ObjectClass *oc, void *data)
pc->realize = nvme_realize;
pc->exit = nvme_exit;
pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
- pc->vendor_id = PCI_VENDOR_ID_INTEL;
- pc->device_id = 0x5845;
pc->revision = 2;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
diff --git a/hw/core/machine.c b/hw/core/machine.c
index ea26d612374d..944120cf19c8 100644
--- a/hw/core/machine.c
+++ b/hw/core/machine.c
@@ -34,6 +34,7 @@ GlobalProperty hw_compat_5_1[] = {
{ "vhost-user-scsi", "num_queues", "1"},
{ "virtio-blk-device", "num-queues", "1"},
{ "virtio-scsi-device", "num_queues", "1"},
+ { "nvme", "use-intel-id", "on"},
};
const size_t hw_compat_5_1_len = G_N_ELEMENTS(hw_compat_5_1);
--
2.28.0
- [PATCH v3 10/17] hw/block/nvme: default request status to success, (continued)
- [PATCH v3 10/17] hw/block/nvme: default request status to success, Klaus Jensen, 2020/09/22
- [PATCH v3 03/17] hw/block/nvme: handle dma errors, Klaus Jensen, 2020/09/22
- [PATCH v3 07/17] hw/block/nvme: fix endian conversion, Klaus Jensen, 2020/09/22
- [PATCH v3 09/17] hw/block/nvme: refactor aio submission, Klaus Jensen, 2020/09/22
- [PATCH v3 11/17] hw/block/nvme: harden cmb access, Klaus Jensen, 2020/09/22
- [PATCH v3 12/17] hw/block/nvme: add support for scatter gather lists, Klaus Jensen, 2020/09/22
- [PATCH v3 14/17] hw/block/nvme: refactor identify active namespace id list, Klaus Jensen, 2020/09/22
- [PATCH v3 13/17] hw/block/nvme: add support for sgl bit bucket descriptor, Klaus Jensen, 2020/09/22
- [PATCH v3 16/17] pci: allocate pci id for nvme, Klaus Jensen, 2020/09/22
- [PATCH v3 15/17] hw/block/nvme: support multiple namespaces, Klaus Jensen, 2020/09/22
- [PATCH v3 17/17] hw/block/nvme: change controller pci id,
Klaus Jensen <=
- Re: [PATCH v3 00/17] hw/block/nvme: multiple namespaces support, Keith Busch, 2020/09/22
- Re: [PATCH v3 00/17] hw/block/nvme: multiple namespaces support, Klaus Jensen, 2020/09/23