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[PULL 21/66] target/mips: Add !CONFIG_USER_ONLY comment after #endif
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 21/66] target/mips: Add !CONFIG_USER_ONLY comment after #endif |
Date: |
Thu, 7 Jan 2021 23:22:08 +0100 |
To help understand ifdef'ry, add comment after #endif.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-4-f4bug@amsat.org>
---
target/mips/helper.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index d1b6bb6fb23..92bd3fb8550 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -455,7 +455,8 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong
val)
}
}
}
-#endif
+
+#endif /* !CONFIG_USER_ONLY */
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
int rw, int tlb_error)
@@ -537,6 +538,7 @@ static void raise_mmu_exception(CPUMIPSState *env,
target_ulong address,
}
#if !defined(CONFIG_USER_ONLY)
+
hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
MIPSCPU *cpu = MIPS_CPU(cs);
@@ -550,7 +552,7 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr
addr)
}
return phys_addr;
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
#if !defined(CONFIG_USER_ONLY)
#if !defined(TARGET_MIPS64)
@@ -886,7 +888,7 @@ refill:
return true;
}
#endif
-#endif
+#endif /* !CONFIG_USER_ONLY */
bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
@@ -1088,7 +1090,8 @@ static inline void set_badinstr_registers(CPUMIPSState
*env)
env->CP0_BadInstrP = cpu_ldl_code(env, env->active_tc.PC - 4);
}
}
-#endif
+
+#endif /* !CONFIG_USER_ONLY */
void mips_cpu_do_interrupt(CPUState *cs)
{
@@ -1482,7 +1485,7 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int
use_extra)
}
}
}
-#endif
+#endif /* !CONFIG_USER_ONLY */
void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
uint32_t exception,
--
2.26.2
- [PULL 11/66] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3, (continued)
- [PULL 11/66] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 12/66] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 13/66] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 14/66] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 16/66] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 15/66] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 17/66] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 18/66] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 19/66] target/mips: Inline cpu_state_reset() in mips_cpu_reset(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 20/66] target/mips: Extract FPU helpers to 'fpu_helper.h', Philippe Mathieu-Daudé, 2021/01/07
- [PULL 21/66] target/mips: Add !CONFIG_USER_ONLY comment after #endif,
Philippe Mathieu-Daudé <=
- [PULL 22/66] target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 23/66] target/mips: Move common helpers from helper.c to cpu.c, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 24/66] target/mips: Rename helper.c as tlb_helper.c, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 25/66] target/mips: Fix code style for checkpatch.pl, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 26/66] target/mips: Move mmu_init() functions to tlb_helper.c, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 27/66] target/mips: Rename translate_init.c as cpu-defs.c, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 28/66] target/mips/translate: Extract DisasContext structure, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 29/66] target/mips/translate: Add declarations for generic code, Philippe Mathieu-Daudé, 2021/01/07
- [PULL 30/66] target/mips: Replace gen_exception_err(err=0) by gen_exception_end(), Philippe Mathieu-Daudé, 2021/01/07
- [PULL 31/66] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction, Philippe Mathieu-Daudé, 2021/01/07