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[RFC 03/10] target/riscv: rvb: add cmix/cmov instructions
From: |
Eric Tang |
Subject: |
[RFC 03/10] target/riscv: rvb: add cmix/cmov instructions |
Date: |
Sat, 18 Sep 2021 14:28:09 +0800 |
Signed-off-by: Eric Tang <tangxingxin1008@gmail.com>
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 9eff9d5f5c..989ea3c602 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -43,6 +43,7 @@
&r rd rs1 rs2
&r2 rd rs1
&r2_s rs1 rs2
+&r4 rd rs1 rs2 rs3
&s imm rs1 rs2
&u imm rd
&shift shamt rs1 rd
@@ -82,6 +83,7 @@
@r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
+@r4 ..... .. ..... ..... ... ..... ....... &r4 %rs3 %rs2 %rs1 %rd
@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
@@ -693,6 +695,8 @@ sh3add 0010000 .......... 110 ..... 0110011 @r
clmul 0000101 .......... 001 ..... 0110011 @r
clmulh 0000101 .......... 011 ..... 0110011 @r
clmulr 0000101 .......... 010 ..... 0110011 @r
+cmix .....11 .......... 001 ..... 0110011 @r4
+cmov .....11 .......... 101 ..... 0110011 @r4
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 1d999929de..ebcbb341cb 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -332,6 +332,32 @@ GEN_TRANS_CLMUL(clmul)
GEN_TRANS_CLMUL(clmulh)
GEN_TRANS_CLMUL(clmulr)
+static void gen_cmix(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3)
+{
+ tcg_gen_and_tl(arg1, arg1, arg2);
+ tcg_gen_not_tl(arg2, arg2);
+ tcg_gen_and_tl(arg3, arg3, arg2);
+ tcg_gen_or_tl(ret, arg1, arg3);
+}
+
+static void gen_cmov(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3)
+{
+ TCGv zero = tcg_const_tl(0);
+ tcg_gen_movcond_tl(TCG_COND_NE, ret, arg2, zero, arg1, arg3);
+}
+
+static bool trans_cmix(DisasContext *ctx, arg_cmix *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_quat(ctx, a, EXT_NONE, gen_cmix);
+}
+
+static bool trans_cmov(DisasContext *ctx, arg_cmov *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_quat(ctx, a, EXT_NONE, gen_cmov);
+}
+
#define GEN_SHADD(SHAMT) \
static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
{ \
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 74b33fa3c9..0a62666ce7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -395,6 +395,20 @@ static bool gen_arith(DisasContext *ctx, arg_r *a,
DisasExtend ext,
return true;
}
+static bool gen_quat(DisasContext *ctx, arg_r4 *a, DisasExtend ext,
+ void (*func)(TCGv, TCGv, TCGv, TCGv))
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = get_gpr(ctx, a->rs2, ext);
+ TCGv src3 = get_gpr(ctx, a->rs3, ext);
+
+ func(dest, src1, src2, src3);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ return true;
+}
+
static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
void (*func)(TCGv, TCGv, target_long))
{
--
2.17.1
- [RFC 00/10] add the rest of riscv bitmapip-0.93 instructions, Eric Tang, 2021/09/18
- [RFC 01/10] target/riscv: rvb: fixed an error about srow/sroiw instructions, Eric Tang, 2021/09/18
- [RFC 02/10] target/riscv: rvb: add carry-less multiply instructions, Eric Tang, 2021/09/18
- [RFC 03/10] target/riscv: rvb: add cmix/cmov instructions,
Eric Tang <=
- [RFC 04/10] target/riscv: rvb: add generalized shuffle instructions, Eric Tang, 2021/09/18
- [RFC 05/10] target/riscv: rvb: add crossbar permutation instructions, Eric Tang, 2021/09/18
- [RFC 06/10] target/riscv: rvb: add bfp/bfpw instructions, Eric Tang, 2021/09/18
- [RFC 07/10] target/riscv: rvb: add CRC instructions, Eric Tang, 2021/09/18
- [RFC 08/10] target/riscv: rvb: add bit-matrix instructions, Eric Tang, 2021/09/18
- [RFC 09/10] target/riscv: rvb: fixed an issue about clzw instruction, Eric Tang, 2021/09/18
- [RFC 10/10] target/riscv: rvb: add funnel shfit instructions, Eric Tang, 2021/09/18
- Re: [RFC 00/10] add the rest of riscv bitmapip-0.93 instructions, Alistair Francis, 2021/09/24