[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[RFC 08/10] target/riscv: rvb: add bit-matrix instructions
From: |
Eric Tang |
Subject: |
[RFC 08/10] target/riscv: rvb: add bit-matrix instructions |
Date: |
Sat, 18 Sep 2021 14:28:14 +0800 |
Signed-off-by: Eric Tang <tangxingxin1008@gmail.com>
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index 469145ffa9..e936444c12 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -327,3 +327,78 @@ target_ulong HELPER(crc32c_d)(target_ulong rs1)
{
return do_crc32c(rs1, 64);
}
+
+static target_ulong do_bmatflip(target_ulong rs1,
+ int bits)
+{
+ target_ulong x = rs1;
+ for (int i = 0; i < 3; i++) {
+ x = do_shfl(x, 31, bits);
+ }
+ return x;
+}
+
+static target_ulong do_bmatxor(target_ulong rs1,
+ target_ulong rs2,
+ int bits)
+{
+ int i;
+ uint8_t u[8];
+ uint8_t v[8];
+ uint64_t x = 0;
+
+ target_ulong rs2t = do_bmatflip(rs2, bits);
+
+ for (i = 0; i < 8; i++) {
+ u[i] = rs1 >> (i * 8);
+ v[i] = rs2t >> (i * 8);
+ }
+
+ for (int i = 0; i < 64; i++) {
+ if (__builtin_popcount(u[i / 8] & v[i % 8]) & 1) {
+ x |= 1LL << i;
+ }
+ }
+
+ return x;
+}
+
+static target_ulong do_bmator(target_ulong rs1,
+ target_ulong rs2,
+ int bits)
+{
+ int i;
+ uint8_t u[8];
+ uint8_t v[8];
+ uint64_t x = 0;
+
+ target_ulong rs2t = do_bmatflip(rs2, bits);
+
+ for (i = 0; i < 8; i++) {
+ u[i] = rs1 >> (i * 8);
+ v[i] = rs2t >> (i * 8);
+ }
+
+ for (int i = 0; i < 64; i++) {
+ if ((u[i / 8] & v[i % 8]) != 0) {
+ x |= 1LL << i;
+ }
+ }
+
+ return x;
+}
+
+target_ulong HELPER(bmatflip)(target_ulong rs1)
+{
+ return do_bmatflip(rs1, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(bmatxor)(target_ulong rs1, target_ulong rs2)
+{
+ return do_bmatxor(rs1, rs2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(bmator)(target_ulong rs1, target_ulong rs2)
+{
+ return do_bmator(rs1, rs2, TARGET_LONG_BITS);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 9654d6f7a7..8c8fb71bb4 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -84,6 +84,9 @@ DEF_HELPER_FLAGS_1(crc32c_b, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(crc32c_h, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(crc32c_w, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(crc32c_d, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_2(bmatxor, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(bmator, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_1(bmatflip, TCG_CALL_NO_RWG_SE, tl, tl)
/* Special functions */
DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b08e38823b..73f956486b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -730,6 +730,7 @@ unshfli 000010 ........... 101 ..... 0010011 @sh6
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
+bmatflip 0110000 00011 ..... 001 ..... 0010011 @r2
packw 0000100 .......... 100 ..... 0111011 @r
packuw 0100100 .......... 100 ..... 0111011 @r
@@ -751,6 +752,8 @@ shflw 0000100 .......... 001 ..... 0111011 @r
unshflw 0000100 .......... 101 ..... 0111011 @r
xperm_w 0010100 .......... 000 ..... 0110011 @r
bfpw 0100100 .......... 111 ..... 0111011 @r
+bmator 0000100 .......... 011 ..... 0110011 @r
+bmatxor 0100100 .......... 011 ..... 0110011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 0d734bfd10..39ca5a573f 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -805,3 +805,24 @@ static bool trans_bfpw(DisasContext *ctx, arg_bfpw *a)
ctx->w = true;
return gen_arith(ctx, a, EXT_NONE, gen_helper_bfpw);
}
+
+static bool trans_bmatflip(DisasContext *ctx, arg_bmatflip *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_unary(ctx, a, EXT_NONE, gen_helper_bmatflip);
+}
+
+static bool trans_bmatxor(DisasContext *ctx, arg_bmatxor *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_bmatxor);
+}
+
+static bool trans_bmator(DisasContext *ctx, arg_bmator *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, EXT_NONE, gen_helper_bmator);
+}
--
2.17.1
- [RFC 00/10] add the rest of riscv bitmapip-0.93 instructions, Eric Tang, 2021/09/18
- [RFC 01/10] target/riscv: rvb: fixed an error about srow/sroiw instructions, Eric Tang, 2021/09/18
- [RFC 02/10] target/riscv: rvb: add carry-less multiply instructions, Eric Tang, 2021/09/18
- [RFC 03/10] target/riscv: rvb: add cmix/cmov instructions, Eric Tang, 2021/09/18
- [RFC 04/10] target/riscv: rvb: add generalized shuffle instructions, Eric Tang, 2021/09/18
- [RFC 05/10] target/riscv: rvb: add crossbar permutation instructions, Eric Tang, 2021/09/18
- [RFC 06/10] target/riscv: rvb: add bfp/bfpw instructions, Eric Tang, 2021/09/18
- [RFC 07/10] target/riscv: rvb: add CRC instructions, Eric Tang, 2021/09/18
- [RFC 08/10] target/riscv: rvb: add bit-matrix instructions,
Eric Tang <=
- [RFC 09/10] target/riscv: rvb: fixed an issue about clzw instruction, Eric Tang, 2021/09/18
- [RFC 10/10] target/riscv: rvb: add funnel shfit instructions, Eric Tang, 2021/09/18
- Re: [RFC 00/10] add the rest of riscv bitmapip-0.93 instructions, Alistair Francis, 2021/09/24