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[PATCH 09/30] tcg/loongarch: Implement tcg_out_mov and tcg_out_movi
From: |
WANG Xuerui |
Subject: |
[PATCH 09/30] tcg/loongarch: Implement tcg_out_mov and tcg_out_movi |
Date: |
Mon, 20 Sep 2021 16:04:30 +0800 |
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
tcg/loongarch/tcg-target.c.inc | 73 ++++++++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc
index 71564e3246..60783d7ddc 100644
--- a/tcg/loongarch/tcg-target.c.inc
+++ b/tcg/loongarch/tcg-target.c.inc
@@ -261,6 +261,77 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
tcg_out_opc_dbar(s, 0);
}
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+{
+ if (ret == arg) {
+ return true;
+ }
+ switch (type) {
+ case TCG_TYPE_I32:
+ case TCG_TYPE_I64:
+ /*
+ * Conventional register-register move used in LoongArch is
+ * `or dst, src, zero`.
+ */
+ tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
+ tcg_target_long val)
+{
+ tcg_target_long low, upper, higher, top;
+
+ if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
+ val = (int32_t)val;
+ }
+
+ /* Single-instruction cases. */
+ low = sextreg(val, 0, 12);
+ if (low == val) {
+ /* val fits in simm12: addi.w rd, zero, val */
+ tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val);
+ return;
+ }
+ if (0x800 <= val && val <= 0xfff) {
+ /* val fits in uimm12: ori rd, zero, val */
+ tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val);
+ return;
+ }
+
+ /* Chop upper bits into 3 immediate-field-sized segments respectively. */
+ upper = (val >> 12) & 0xfffff;
+ higher = (val >> 32) & 0xfffff;
+ top = val >> 52;
+
+ tcg_out_opc_lu12i_w(s, rd, upper);
+ if (low != 0) {
+ tcg_out_opc_ori(s, rd, rd, low);
+ }
+
+ if (sextreg(val, 0, 32) == val) {
+ /*
+ * Fits in 32-bits, upper bits are already properly sign-extended by
+ * lu12i.w.
+ */
+ return;
+ }
+ tcg_out_opc_cu32i_d(s, rd, higher);
+
+ if (sextreg(val, 0, 52) == val) {
+ /*
+ * Fits in 52-bits, upper bits are already properly sign-extended by
+ * cu32i.d.
+ */
+ return;
+ }
+ tcg_out_opc_cu52i_d(s, rd, rd, top);
+}
+
/*
* Entry-points
*/
@@ -276,6 +347,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_mb(s, a0);
break;
+ case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_mov_i64:
default:
g_assert_not_reached();
}
--
2.33.0
- [PATCH 03/30] tcg/loongarch: Add the tcg-target.h file, (continued)
- [PATCH 22/30] tcg/loongarch: Implement simple load/store ops, WANG Xuerui, 2021/09/20
- [PATCH 26/30] tcg/loongarch: Implement tcg_target_init, WANG Xuerui, 2021/09/20
- [PATCH 29/30] linux-user: Add host dependency for 64-bit LoongArch, WANG Xuerui, 2021/09/20
- [PATCH 09/30] tcg/loongarch: Implement tcg_out_mov and tcg_out_movi,
WANG Xuerui <=
- [PATCH 01/30] elf: Add machine type value for LoongArch, WANG Xuerui, 2021/09/20
- [PATCH 30/30] accel/tcg/user-exec: Implement CPU-specific signal handler for LoongArch hosts, WANG Xuerui, 2021/09/20
- [PATCH 25/30] tcg/loongarch: Implement exit_tb/goto_tb, WANG Xuerui, 2021/09/20
- [PATCH 05/30] tcg/loongarch: Add register names, allocation order and input/output sets, WANG Xuerui, 2021/09/20