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[PATCH v2 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi
From: |
WANG Xuerui |
Subject: |
[PATCH v2 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi |
Date: |
Wed, 22 Sep 2021 04:18:54 +0800 |
Signed-off-by: WANG Xuerui <git@xen0n.name>
---
tcg/loongarch64/tcg-target.c.inc | 89 ++++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 338b772732..e4e7e5e903 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -247,6 +247,93 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
tcg_out_opc_dbar(s, 0);
}
+static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+{
+ if (ret == arg) {
+ return true;
+ }
+ switch (type) {
+ case TCG_TYPE_I32:
+ case TCG_TYPE_I64:
+ /*
+ * Conventional register-register move used in LoongArch is
+ * `or dst, src, zero`.
+ */
+ tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
+ tcg_target_long val)
+{
+ if (type == TCG_TYPE_I32) {
+ val = (int32_t)val;
+ }
+
+ /* Single-instruction cases. */
+ tcg_target_long low = sextreg(val, 0, 12);
+ if (low == val) {
+ /* val fits in simm12: addi.w rd, zero, val */
+ tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val);
+ return;
+ }
+ if (0x800 <= val && val <= 0xfff) {
+ /* val fits in uimm12: ori rd, zero, val */
+ tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val);
+ return;
+ }
+
+ /* Test for PC-relative values that can be loaded faster. */
+ intptr_t pc_offset = val - (uintptr_t)s->code_ptr;
+ if (pc_offset == sextreg(pc_offset, 0, 22) && (pc_offset & 3) == 0) {
+ tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2);
+ return;
+ }
+ if (pc_offset == (int32_t)pc_offset) {
+ tcg_target_long lo = sextreg(pc_offset, 0, 12);
+ tcg_target_long hi = pc_offset - lo;
+ tcg_out_opc_pcaddu12i(s, rd, hi >> 12);
+ tcg_out_opc_addi_d(s, rd, rd, lo);
+ return;
+ }
+
+ /*
+ * Slow path: at most lu12i.w + ori + cu32i.d + cu52i.d.
+ *
+ * Chop upper bits into 3 immediate-field-sized segments respectively.
+ */
+ tcg_target_long upper = (val >> 12) & 0xfffff;
+ tcg_target_long higher = (val >> 32) & 0xfffff;
+ tcg_target_long top = val >> 52;
+
+ tcg_out_opc_lu12i_w(s, rd, upper);
+ if (low != 0) {
+ tcg_out_opc_ori(s, rd, rd, low & 0xfff);
+ }
+
+ if (sextreg(val, 0, 32) == val) {
+ /*
+ * Fits in 32-bits, upper bits are already properly sign-extended by
+ * lu12i.w.
+ */
+ return;
+ }
+ tcg_out_opc_cu32i_d(s, rd, higher);
+
+ if (sextreg(val, 0, 52) == val) {
+ /*
+ * Fits in 52-bits, upper bits are already properly sign-extended by
+ * cu32i.d.
+ */
+ return;
+ }
+ tcg_out_opc_cu52i_d(s, rd, rd, top);
+}
+
/*
* Entry-points
*/
@@ -262,6 +349,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_mb(s, a0);
break;
+ case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_mov_i64:
default:
g_assert_not_reached();
}
--
2.33.0
- [PATCH v2 00/30] LoongArch64 port of QEMU TCG, WANG Xuerui, 2021/09/21
- [PATCH v2 01/30] elf: Add machine type value for LoongArch, WANG Xuerui, 2021/09/21
- [PATCH v2 02/30] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer, WANG Xuerui, 2021/09/21
- [PATCH v2 07/30] tcg/loongarch64: Implement necessary relocation operations, WANG Xuerui, 2021/09/21
- [PATCH v2 06/30] tcg/loongarch64: Define the operand constraints, WANG Xuerui, 2021/09/21
- [PATCH v2 03/30] tcg/loongarch64: Add the tcg-target.h file, WANG Xuerui, 2021/09/21
- [PATCH v2 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi,
WANG Xuerui <=
[PATCH v2 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers, WANG Xuerui, 2021/09/21
[PATCH v2 08/30] tcg/loongarch64: Implement the memory barrier op, WANG Xuerui, 2021/09/21
[PATCH v2 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets, WANG Xuerui, 2021/09/21
[PATCH v2 10/30] tcg/loongarch64: Implement goto_ptr, WANG Xuerui, 2021/09/21
[PATCH v2 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc/eqv ops, WANG Xuerui, 2021/09/21