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[PULL 19/23] target/arm: Reformat comments in add_cpreg_to_hashtable
From: |
Peter Maydell |
Subject: |
[PULL 19/23] target/arm: Reformat comments in add_cpreg_to_hashtable |
Date: |
Thu, 5 May 2022 10:11:43 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Put the block comments into the current coding style.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index fa1e7bd462c..81612952f3a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8496,15 +8496,16 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error
**errp)
return cpu_list;
}
+/*
+ * Private utility function for define_one_arm_cp_reg_with_opaque():
+ * add a single reginfo struct to the hash table.
+ */
static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
void *opaque, CPState state,
CPSecureState secstate,
int crm, int opc1, int opc2,
const char *name)
{
- /* Private utility function for define_one_arm_cp_reg_with_opaque():
- * add a single reginfo struct to the hash table.
- */
uint32_t key;
ARMCPRegInfo *r2;
bool is64 = r->type & ARM_CP_64BIT;
@@ -8568,7 +8569,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
ARMCPRegInfo *r,
isbanked = r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1];
if (isbanked) {
- /* Register is banked (using both entries in array).
+ /*
+ * Register is banked (using both entries in array).
* Overwriting fieldoffset as the array is only used to define
* banked registers but later only fieldoffset is used.
*/
@@ -8577,7 +8579,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
ARMCPRegInfo *r,
if (state == ARM_CP_STATE_AA32) {
if (isbanked) {
- /* If the register is banked then we don't need to migrate or
+ /*
+ * If the register is banked then we don't need to migrate or
* reset the 32-bit instance in certain cases:
*
* 1) If the register has both 32-bit and 64-bit instances then we
@@ -8592,8 +8595,9 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
ARMCPRegInfo *r,
r2->type |= ARM_CP_ALIAS;
}
} else if ((secstate != r->secure) && !ns) {
- /* The register is not banked so we only want to allow migration of
- * the non-secure instance.
+ /*
+ * The register is not banked so we only want to allow migration
+ * of the non-secure instance.
*/
r2->type |= ARM_CP_ALIAS;
}
@@ -8607,7 +8611,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
ARMCPRegInfo *r,
}
}
- /* By convention, for wildcarded registers only the first
+ /*
+ * By convention, for wildcarded registers only the first
* entry is used for migration; the others are marked as
* ALIAS so we don't try to transfer the register
* multiple times. Special registers (ie NOP/WFI) are
@@ -8622,7 +8627,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
ARMCPRegInfo *r,
r2->type |= ARM_CP_ALIAS | ARM_CP_NO_GDB;
}
- /* Check that raw accesses are either forbidden or handled. Note that
+ /*
+ * Check that raw accesses are either forbidden or handled. Note that
* we can't assert this earlier because the setup of fieldoffset for
* banked registers has to be done first.
*/
--
2.25.1
- [PULL 08/23] target/arm: Change cpreg access permissions to enum, (continued)
- [PULL 08/23] target/arm: Change cpreg access permissions to enum, Peter Maydell, 2022/05/05
- [PULL 07/23] target/arm: Avoid bare abort() or assert(0), Peter Maydell, 2022/05/05
- [PULL 10/23] target/arm: Name CPSecureState type, Peter Maydell, 2022/05/05
- [PULL 09/23] target/arm: Name CPState type, Peter Maydell, 2022/05/05
- [PULL 04/23] target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h, Peter Maydell, 2022/05/05
- [PULL 13/23] target/arm: Merge allocation of the cpreg and its name, Peter Maydell, 2022/05/05
- [PULL 15/23] target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable, Peter Maydell, 2022/05/05
- [PULL 11/23] target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases, Peter Maydell, 2022/05/05
- [PULL 17/23] target/arm: Hoist isbanked computation in add_cpreg_to_hashtable, Peter Maydell, 2022/05/05
- [PULL 18/23] target/arm: Perform override check early in add_cpreg_to_hashtable, Peter Maydell, 2022/05/05
- [PULL 19/23] target/arm: Reformat comments in add_cpreg_to_hashtable,
Peter Maydell <=
- [PULL 12/23] target/arm: Store cpregs key in the hash table directly, Peter Maydell, 2022/05/05
- [PULL 14/23] target/arm: Hoist computation of key in add_cpreg_to_hashtable, Peter Maydell, 2022/05/05
- [PULL 16/23] target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable, Peter Maydell, 2022/05/05
- [PULL 20/23] target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable, Peter Maydell, 2022/05/05
- [PULL 22/23] target/arm: Add isar_feature_{aa64,any}_ras, Peter Maydell, 2022/05/05
- [PULL 23/23] target/arm: read access to performance counters from EL0, Peter Maydell, 2022/05/05
- [PULL 21/23] target/arm: Add isar predicates for FEAT_Debugv8p2, Peter Maydell, 2022/05/05
- Re: [PULL 00/23] target-arm queue, Richard Henderson, 2022/05/05