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[PULL 075/117] target/arm: Reject add/sub w/ shifted byte early
From: |
Peter Maydell |
Subject: |
[PULL 075/117] target/arm: Reject add/sub w/ shifted byte early |
Date: |
Mon, 30 May 2022 17:06:26 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Remove the unparsed extractions in trans_ADD_zzi, trans_SUBR_zzi,
and do_zzi_sat which are intended to reject an 8-bit shift of an
8-bit constant for 8-bit element.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-73-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/sve.decode | 35 ++++++++++++++++++++++++++++-------
target/arm/translate-sve.c | 9 ---------
2 files changed, 28 insertions(+), 16 deletions(-)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index c02da0a0829..8cff63cf257 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -793,13 +793,34 @@ FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
}
# SVE integer add/subtract immediate (unpredicated)
-ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
-SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
-SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
-SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
-UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
-SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
-UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
+{
+ INVALID 00100101 00 100 000 11 1 -------- -----
+ ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
+}
+{
+ INVALID 00100101 00 100 001 11 1 -------- -----
+ SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
+}
+{
+ INVALID 00100101 00 100 011 11 1 -------- -----
+ SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
+}
+{
+ INVALID 00100101 00 100 100 11 1 -------- -----
+ SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
+}
+{
+ INVALID 00100101 00 100 101 11 1 -------- -----
+ UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
+}
+{
+ INVALID 00100101 00 100 110 11 1 -------- -----
+ SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
+}
+{
+ INVALID 00100101 00 100 111 11 1 -------- -----
+ UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
+}
# SVE integer min/max immediate (unpredicated)
SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 14faef05641..bf988cab3eb 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3262,9 +3262,6 @@ static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
static bool trans_ADD_zzi(DisasContext *s, arg_rri_esz *a)
{
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
- return false;
- }
return gen_gvec_fn_arg_zzi(s, tcg_gen_gvec_addi, a);
}
@@ -3305,9 +3302,6 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_esz
*a)
.scalar_first = true }
};
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
- return false;
- }
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd),
@@ -3321,9 +3315,6 @@ TRANS_FEAT(MUL_zzi, aa64_sve, gen_gvec_fn_arg_zzi,
tcg_gen_gvec_muli, a)
static bool do_zzi_sat(DisasContext *s, arg_rri_esz *a, bool u, bool d)
{
- if (a->esz == 0 && extract32(s->insn, 13, 1)) {
- return false;
- }
if (sve_access_check(s)) {
do_sat_addsub_vec(s, a->esz, a->rd, a->rn,
tcg_constant_i64(a->imm), u, d);
--
2.25.1
- [PULL 073/117] target/arm: Use TRANS_FEAT for MUL_zzi, (continued)
- [PULL 073/117] target/arm: Use TRANS_FEAT for MUL_zzi, Peter Maydell, 2022/05/30
- [PULL 074/117] target/arm: Reject dup_i w/ shifted byte early, Peter Maydell, 2022/05/30
- [PULL 094/117] target/arm: Use TRANS_FEAT for FRECPE, FRSQRTE, Peter Maydell, 2022/05/30
- [PULL 095/117] target/arm: Expand frint_fns for MO_8, Peter Maydell, 2022/05/30
- [PULL 096/117] target/arm: Rename do_zpz_ptr to gen_gvec_ool_fpst_arg_zpz, Peter Maydell, 2022/05/30
- [PULL 082/117] target/arm: Move sve check into gen_gvec_fn_ppp, Peter Maydell, 2022/05/30
- [PULL 084/117] target/arm: Use TRANS_FEAT for SEL_zpzz, Peter Maydell, 2022/05/30
- [PULL 086/117] target/arm: Use TRANS_FEAT for FMLA, Peter Maydell, 2022/05/30
- [PULL 092/117] target/arm: Move null function and sve check into do_reduce, Peter Maydell, 2022/05/30
- [PULL 064/117] target/arm: Use TRANS_FEAT for do_clast_fp, Peter Maydell, 2022/05/30
- [PULL 075/117] target/arm: Reject add/sub w/ shifted byte early,
Peter Maydell <=
- [PULL 080/117] target/arm: Introduce gen_gvec_{ptr,fpst}_zzzz, Peter Maydell, 2022/05/30
- [PULL 027/117] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpzi, Peter Maydell, 2022/05/30
- [PULL 079/117] target/arm: Use TRANS_FEAT for do_zzi_ool, Peter Maydell, 2022/05/30
- [PULL 087/117] target/arm: Use TRANS_FEAT for BFMLA, Peter Maydell, 2022/05/30
- [PULL 051/117] target/arm: Move sve check into do_index, Peter Maydell, 2022/05/30
- [PULL 066/117] target/arm: Use TRANS_FEAT for do_last_fp, Peter Maydell, 2022/05/30
- [PULL 072/117] target/arm: Use TRANS_FEAT for do_brk2, do_brk3, Peter Maydell, 2022/05/30
- [PULL 071/117] target/arm: Use TRANS_FEAT for do_ppzi_flags, Peter Maydell, 2022/05/30
- [PULL 076/117] target/arm: Reject copy w/ shifted byte early, Peter Maydell, 2022/05/30
- [PULL 081/117] target/arm: Use TRANS_FEAT for FMMLA, Peter Maydell, 2022/05/30