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[PULL 01/60] pnv/psi: Allow access to PSI registers through xscom
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 01/60] pnv/psi: Allow access to PSI registers through xscom |
Date: |
Fri, 7 Jul 2023 08:30:09 -0300 |
From: Frederic Barrat <fbarrat@linux.ibm.com>
skiboot only uses mmio to access the PSI registers (once the BAR is
set) but we don't have any reason to block the accesses through
xscom. This patch enables xscom access to the PSI registers. It
converts the xscom addresses to mmio addresses, which requires a bit
of care for the PSIHB, then reuse the existing mmio ops.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230630102609.193214-1-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/pnv_psi.c | 31 +++++++++++++++++++++----------
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 8aa09ab26b..46da58dff8 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -121,8 +121,12 @@
#define PSIHB9_BAR_MASK 0x00fffffffff00000ull
#define PSIHB9_FSPBAR_MASK 0x00ffffff00000000ull
+/* mmio address to xscom address */
#define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR)
+/* xscom address to mmio address */
+#define PSIHB_MMIO(reg) ((reg - PSIHB_XSCOM_BAR) << 3)
+
static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
{
PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi);
@@ -769,24 +773,31 @@ static const MemoryRegionOps pnv_psi_p9_mmio_ops = {
static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size)
{
- /* No read are expected */
- qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom read at 0x%" PRIx64 "\n", addr);
- return -1;
+ uint32_t reg = addr >> 3;
+ uint64_t val = -1;
+
+ if (reg < PSIHB_XSCOM_BAR) {
+ /* FIR, not modeled */
+ qemu_log_mask(LOG_UNIMP, "PSI: xscom read at 0x%08x\n", reg);
+ } else {
+ val = pnv_psi_p9_mmio_read(opaque, PSIHB_MMIO(reg), size);
+ }
+ return val;
}
static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
PnvPsi *psi = PNV_PSI(opaque);
+ uint32_t reg = addr >> 3;
- /* XSCOM is only used to set the PSIHB MMIO region */
- switch (addr >> 3) {
- case PSIHB_XSCOM_BAR:
+ if (reg < PSIHB_XSCOM_BAR) {
+ /* FIR, not modeled */
+ qemu_log_mask(LOG_UNIMP, "PSI: xscom write at 0x%08x\n", reg);
+ } else if (reg == PSIHB_XSCOM_BAR) {
pnv_psi_set_bar(psi, val);
- break;
- default:
- qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom write at 0x%" PRIx64 "\n",
- addr);
+ } else {
+ pnv_psi_p9_mmio_write(opaque, PSIHB_MMIO(reg), val, size);
}
}
--
2.41.0
- [PULL 00/60] ppc queue, Daniel Henrique Barboza, 2023/07/07
- [PULL 02/60] target/ppc: Make HDECR underflow edge triggered, Daniel Henrique Barboza, 2023/07/07
- [PULL 01/60] pnv/psi: Allow access to PSI registers through xscom,
Daniel Henrique Barboza <=
- [PULL 03/60] hw/ppc: Fix clock update drift, Daniel Henrique Barboza, 2023/07/07
- [PULL 06/60] target/ppc: Tidy POWER book4 SPR registration, Daniel Henrique Barboza, 2023/07/07
- [PULL 05/60] mv64361: Add dummy gigabit ethernet PHY access registers, Daniel Henrique Barboza, 2023/07/07
- [PULL 04/60] target/ppc: Only generate decodetree files when TCG is enabled, Daniel Henrique Barboza, 2023/07/07
- [PULL 07/60] target/ppc: Add TFMR SPR implementation with read and write helpers, Daniel Henrique Barboza, 2023/07/07
- [PULL 08/60] sungem: Add WOL MMIO, Daniel Henrique Barboza, 2023/07/07
- [PULL 09/60] target/ppc: Fix icount access for some hypervisor instructions, Daniel Henrique Barboza, 2023/07/07
- [PULL 10/60] tests/avocado: record_replay test for ppc powernv machine, Daniel Henrique Barboza, 2023/07/07
- [PULL 11/60] pnv/xive2: Allow indirect TIMA accesses of all sizes, Daniel Henrique Barboza, 2023/07/07
- [PULL 12/60] target/ppc: Remove some superfluous parentheses, Daniel Henrique Barboza, 2023/07/07