[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 07/60] target/ppc: Add TFMR SPR implementation with read and write
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 07/60] target/ppc: Add TFMR SPR implementation with read and write helpers |
Date: |
Fri, 7 Jul 2023 08:30:15 -0300 |
From: Nicholas Piggin <npiggin@gmail.com>
TFMR is the Time Facility Management Register which is specific to
POWER CPUs, and used for the purpose of timebase management (generally
by firmware, not the OS).
Add helpers for the TFMR register, which will form part of the core
timebase facility model in future but for now behaviour is unchanged.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20230625120317.13877-3-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/cpu_init.c | 2 +-
target/ppc/helper.h | 2 ++
target/ppc/spr_common.h | 2 ++
target/ppc/timebase_helper.c | 13 +++++++++++++
target/ppc/translate.c | 10 ++++++++++
5 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index dc93581dd3..5f4969664e 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5658,7 +5658,7 @@ static void register_power_common_book4_sprs(CPUPPCState
*env)
spr_register_hv(env, SPR_TFMR, "TFMR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
+ &spr_read_tfmr, &spr_write_tfmr,
0x00000000);
#endif
}
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index fda40b8a60..828f7844c8 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -722,6 +722,8 @@ DEF_HELPER_FLAGS_1(load_dpdes, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_2(store_dpdes, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_2(book3s_msgsndp, void, env, tl)
DEF_HELPER_2(book3s_msgclrp, void, env, tl)
+DEF_HELPER_1(load_tfmr, tl, env)
+DEF_HELPER_2(store_tfmr, void, env, tl)
#endif
DEF_HELPER_2(store_sdr1, void, env, tl)
DEF_HELPER_2(store_pidr, void, env, tl)
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index 4c0f2bed77..fbf52123b5 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -194,6 +194,8 @@ void spr_write_ebb(DisasContext *ctx, int sprn, int gprn);
void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn);
void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn);
void spr_write_hmer(DisasContext *ctx, int sprn, int gprn);
+void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn);
+void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn);
void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn);
void spr_read_dexcr_ureg(DisasContext *ctx, int gprn, int sprn);
#endif
diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c
index b80f56af7e..08a6b47ee0 100644
--- a/target/ppc/timebase_helper.c
+++ b/target/ppc/timebase_helper.c
@@ -144,6 +144,19 @@ void helper_store_booke_tsr(CPUPPCState *env, target_ulong
val)
store_booke_tsr(env, val);
}
+#if defined(TARGET_PPC64)
+/* POWER processor Timebase Facility */
+target_ulong helper_load_tfmr(CPUPPCState *env)
+{
+ return env->spr[SPR_TFMR];
+}
+
+void helper_store_tfmr(CPUPPCState *env, target_ulong val)
+{
+ env->spr[SPR_TFMR] = val;
+}
+#endif
+
/*****************************************************************************/
/* Embedded PowerPC specific helpers */
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 372ee600b2..599bd4b4f9 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1175,6 +1175,16 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int
gprn)
spr_store_dump_spr(sprn);
}
+void spr_read_tfmr(DisasContext *ctx, int gprn, int sprn)
+{
+ gen_helper_load_tfmr(cpu_gpr[gprn], cpu_env);
+}
+
+void spr_write_tfmr(DisasContext *ctx, int sprn, int gprn)
+{
+ gen_helper_store_tfmr(cpu_env, cpu_gpr[gprn]);
+}
+
void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]);
--
2.41.0
- [PULL 00/60] ppc queue, Daniel Henrique Barboza, 2023/07/07
- [PULL 02/60] target/ppc: Make HDECR underflow edge triggered, Daniel Henrique Barboza, 2023/07/07
- [PULL 01/60] pnv/psi: Allow access to PSI registers through xscom, Daniel Henrique Barboza, 2023/07/07
- [PULL 03/60] hw/ppc: Fix clock update drift, Daniel Henrique Barboza, 2023/07/07
- [PULL 06/60] target/ppc: Tidy POWER book4 SPR registration, Daniel Henrique Barboza, 2023/07/07
- [PULL 05/60] mv64361: Add dummy gigabit ethernet PHY access registers, Daniel Henrique Barboza, 2023/07/07
- [PULL 04/60] target/ppc: Only generate decodetree files when TCG is enabled, Daniel Henrique Barboza, 2023/07/07
- [PULL 07/60] target/ppc: Add TFMR SPR implementation with read and write helpers,
Daniel Henrique Barboza <=
- [PULL 08/60] sungem: Add WOL MMIO, Daniel Henrique Barboza, 2023/07/07
- [PULL 09/60] target/ppc: Fix icount access for some hypervisor instructions, Daniel Henrique Barboza, 2023/07/07
- [PULL 10/60] tests/avocado: record_replay test for ppc powernv machine, Daniel Henrique Barboza, 2023/07/07
- [PULL 11/60] pnv/xive2: Allow indirect TIMA accesses of all sizes, Daniel Henrique Barboza, 2023/07/07
- [PULL 12/60] target/ppc: Remove some superfluous parentheses, Daniel Henrique Barboza, 2023/07/07
- [PULL 13/60] target/ppc: Remove unneeded parameter from powerpc_reset_wakeup(), Daniel Henrique Barboza, 2023/07/07
- [PULL 14/60] target/ppc: Move common check in exception handlers to a function, Daniel Henrique Barboza, 2023/07/07
- [PULL 15/60] target/ppc: Remove some more local CPUState variables only used once, Daniel Henrique Barboza, 2023/07/07
- [PULL 16/60] target/ppd: Remove unused define, Daniel Henrique Barboza, 2023/07/07
- [PULL 17/60] target/ppc: Get CPUState in one step, Daniel Henrique Barboza, 2023/07/07