Re: [PATCH v5 04/60] target/riscv: add vector configure instruction

[Alistair Francis]

On Thu, Mar 12, 2020 at 3:00 PM LIU Zhiwei <address@hidden> wrote:
>
>
>
> On 2020/3/13 5:23, Alistair Francis wrote:
> > On Thu, Mar 12, 2020 at 8:07 AM LIU Zhiwei <address@hidden> wrote:
> >> vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags
> >> should update after configure instructions. The (ill, lmul, sew ) of vtype
> >> and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags.
> >>
> >> Signed-off-by: LIU Zhiwei <address@hidden>
> >> ---
> >>   target/riscv/Makefile.objs              |  2 +-
> >>   target/riscv/cpu.h                      | 63 ++++++++++++++++++----
> >>   target/riscv/helper.h                   |  2 +
> >>   target/riscv/insn32.decode              |  5 ++
> >>   target/riscv/insn_trans/trans_rvv.inc.c | 69 +++++++++++++++++++++++++
> >>   target/riscv/translate.c                | 17 +++++-
> >>   target/riscv/vector_helper.c            | 53 +++++++++++++++++++
> >>   7 files changed, 199 insertions(+), 12 deletions(-)
> >>   create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c
> >>   create mode 100644 target/riscv/vector_helper.c
> >>

...

> >> +    gen_get_gpr(s2, a->rs2);
> >> +    gen_helper_vsetvl(dst, cpu_env, s1, s2);
> >> +    gen_set_gpr(a->rd, dst);
> >> +    tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
> >> +    exit_tb(ctx);
> > Why does this
> As the vsetvl will change vtype, the tb flags of the instructions next
> to the vsetvl
> will change(some tb flags  are from vtype, like LMUL).
> >
> >> +    ctx->base.is_jmp = DISAS_NORETURN;
> >> +
> >> +    tcg_temp_free(s1);
> >> +    tcg_temp_free(s2);
> >> +    tcg_temp_free(dst);
> >> +    return true;
> >> +}
> >> +
> >> +static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli * a)
> >> +{
> >> +    TCGv s1, s2, dst;
> >> +    s2 = tcg_const_tl(a->zimm);
> >> +    dst = tcg_temp_new();
> >> +
> >> +    /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
> >> +    if (a->rs1 == 0) {
> >> +        /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> >> +        s1 = tcg_const_tl(RV_VLEN_MAX);
> >> +    } else {
> >> +        s1 = tcg_temp_new();
> >> +        gen_get_gpr(s1, a->rs1);
> >> +    }
> >> +    gen_helper_vsetvl(dst, cpu_env, s1, s2);
> >> +    gen_set_gpr(a->rd, dst);
> >> +    gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
> > Need to be different to this?
> Although vsetvli will also change vtype, the vtype will be a constant.
> So the tb flags of  the instruction(A) next to
> it will always be same with the tb flags at first translation of A.
> That's why gen_goto_tb is enough.

Ah ok. Makes sense.

Once you fix the one nit pick I had you can add my reviewed by:

Reviewed-by: Alistair Francis <address@hidden>

Alistair

>
> Zhiwei