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Re: [PATCH v5 05/60] target/riscv: add vector stride load and store inst
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions |
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Date: |
Fri, 13 Mar 2020 18:26:24 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/13/20 2:32 PM, LIU Zhiwei wrote:
>>> +/* check functions */
>>> +static bool vext_check_isa_ill(DisasContext *s, target_ulong isa)
>>> +{
>>> + return !s->vill && ((s->misa & isa) == isa);
>>> +}
>> I don't think we need a new function to check ISA.
> I don't think so.
>
> Although there is a riscv_has_ext(env, isa) in cpu.h, it is not proper in this
> file,
> as it is in translation time and usually DisasContext is used here instead
> of CPURISCVState.
In translate.c we have has_ext() for this purpose.
I think you don't need to test has_ext(s, RVV) at all,
because in cpu_get_tb_cpu_state(), you already tested
RVV, and set VILL if RVV was not present.
Thus testing vill here is sufficient. A comment here
to remind us of that fact would be appropriate.
For those few cases where you have an extension beyond
RVV, e.g. amo_check() I think you should simply use
has_ext() like so:
static bool amo_check(DisasContext *s, arg_rwdvm *a)
{
return (!s->vill &&
has_ext(s, RVA) &&
...);
}
r~
[PATCH v5 05/60] target/riscv: add vector stride load and store instructions, LIU Zhiwei, 2020/03/12
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions,
Richard Henderson <=
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions, LIU Zhiwei, 2020/03/13
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions, Richard Henderson, 2020/03/13
[PATCH v5 06/60] target/riscv: add vector index load and store instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 07/60] target/riscv: add fault-only-first unit stride load, LIU Zhiwei, 2020/03/12
[PATCH v5 08/60] target/riscv: add vector amo operations, LIU Zhiwei, 2020/03/12