[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v5 04/60] target/riscv: add vector configure instruction
|
From: |
Richard Henderson |
|
Subject: |
Re: [PATCH v5 04/60] target/riscv: add vector configure instruction |
|
Date: |
Fri, 13 Mar 2020 18:14:37 -0700 |
|
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl * a)
> +{
> + TCGv s1, s2, dst;
> + s2 = tcg_temp_new();
> + dst = tcg_temp_new();
> +
> + /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
> + if (a->rs1 == 0) {
> + /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> + s1 = tcg_const_tl(RV_VLEN_MAX);
> + } else {
> + s1 = tcg_temp_new();
> + gen_get_gpr(s1, a->rs1);
> + }
> + gen_get_gpr(s2, a->rs2);
> + gen_helper_vsetvl(dst, cpu_env, s1, s2);
> + gen_set_gpr(a->rd, dst);
> + tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
> + exit_tb(ctx);
You can use lookup_and_goto_ptr here. But either way,
Reviewed-by: Richard Henderson <address@hidden>
r~
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions, Richard Henderson, 2020/03/13
[PATCH v5 06/60] target/riscv: add vector index load and store instructions, LIU Zhiwei, 2020/03/12