Re: [PATCH v5 08/60] target/riscv: add vector amo operations

qemu-riscv

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v5 08/60] target/riscv: add vector amo operations

From:	Richard Henderson
Subject:	Re: [PATCH v5 08/60] target/riscv: add vector amo operations
Date:	Fri, 13 Mar 2020 21:28:15 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1

On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +    static gen_helper_amo *const fnsw[9] = {
...
> +    static gen_helper_amo *const fnsd[18] = {
...
> +        fn = fnsw[seq];
> +#ifdef TARGET_RISCV64
> +        if (s->sew == 3) {
> +            fn = fnsd[seq];
> +        }
> +#endif

This indexing is wrong, since for seq == 11 you index past the end of fnsw[].

You need something like

    if (s->sew == 3) {
#ifdef TARGET_RISCV64
        fn = fnsd[seq];
#else
        /* Check done in amo_check(). */
        g_assert_not_reached();
#endif
    } else {
        fn = fnsw[seq];
    }

Otherwise it looks ok.


r~

[Prev in Thread]

Current Thread

[Next in Thread]

[PATCH v5 06/60] target/riscv: add vector index load and store instructions, (continued)
- [PATCH v5 06/60] target/riscv: add vector index load and store instructions, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 06/60] target/riscv: add vector index load and store instructions, Alistair Francis, 2020/03/13
  - Re: [PATCH v5 06/60] target/riscv: add vector index load and store instructions, Richard Henderson, 2020/03/13
- [PATCH v5 07/60] target/riscv: add fault-only-first unit stride load, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 07/60] target/riscv: add fault-only-first unit stride load, Alistair Francis, 2020/03/13
    - Re: [PATCH v5 07/60] target/riscv: add fault-only-first unit stride load, LIU Zhiwei, 2020/03/13
  - Re: [PATCH v5 07/60] target/riscv: add fault-only-first unit stride load, Richard Henderson, 2020/03/13
- [PATCH v5 08/60] target/riscv: add vector amo operations, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 08/60] target/riscv: add vector amo operations, Alistair Francis, 2020/03/13
    - Re: [PATCH v5 08/60] target/riscv: add vector amo operations, LIU Zhiwei, 2020/03/13
  - Re: [PATCH v5 08/60] target/riscv: add vector amo operations, Richard Henderson <=
    - Re: [PATCH v5 08/60] target/riscv: add vector amo operations, LIU Zhiwei, 2020/03/14
- [PATCH v5 09/60] target/riscv: vector single-width integer add and subtract, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 09/60] target/riscv: vector single-width integer add and subtract, Richard Henderson, 2020/03/14
    - Re: [PATCH v5 09/60] target/riscv: vector single-width integer add and subtract, LIU Zhiwei, 2020/03/14
    - Re: [PATCH v5 09/60] target/riscv: vector single-width integer add and subtract, LIU Zhiwei, 2020/03/23
    - Re: [PATCH v5 09/60] target/riscv: vector single-width integer add and subtract, Richard Henderson, 2020/03/23
- [PATCH v5 10/60] target/riscv: vector widening integer add and subtract, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 10/60] target/riscv: vector widening integer add and subtract, Richard Henderson, 2020/03/14
- [PATCH v5 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions, LIU Zhiwei, 2020/03/12
  - Re: [PATCH v5 11/60] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions, Richard Henderson, 2020/03/14

Prev by Date: Re: [PATCH v2 2/2] target/riscv: Add a sifive-e34 cpu type
Next by Date: Re: [PATCH v5 08/60] target/riscv: add vector amo operations
Previous by thread: Re: [PATCH v5 08/60] target/riscv: add vector amo operations
Next by thread: Re: [PATCH v5 08/60] target/riscv: add vector amo operations
Index(es):
- Date
- Thread