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Re: [RFC 07/65] target/riscv: rvv-0.9: add vector context status
From: |
Richard Henderson |
Subject: |
Re: [RFC 07/65] target/riscv: rvv-0.9: add vector context status |
Date: |
Fri, 10 Jul 2020 10:26:27 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 |
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -376,6 +376,7 @@
> #define MSTATUS_SPP 0x00000100
> #define MSTATUS_MPP 0x00001800
> #define MSTATUS_FS 0x00006000
> +#define MSTATUS_VS 0x00000600
> #define MSTATUS_XS 0x00018000
Please sort VS up below SPP, so that the bits are in order.
> @@ -180,6 +180,7 @@ static int write_fcsr(CPURISCVState *env, int csrno,
> target_ulong val)
> return -1;
> }
> env->mstatus |= MSTATUS_FS;
> + env->mstatus |= MSTATUS_VS;
> #endif
> env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
> if (vs(env, csrno) >= 0) {
Does rvv 0.9 still have the vector fields in FCSR, or are they only present in
the new VCSR?
> @@ -420,7 +442,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,
> target_ulong val)
> mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
> MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
> MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
> - MSTATUS_TW;
> + MSTATUS_TW | MSTATUS_VS;
Since 0.7.1 does not have the VS field, you might want to force VS to dirty in
the written mstatus. Correspondingly, you should remove VS from the returned
mstatus in read_mstatus.
You appear to be missing a change to riscv_cpu_swap_hypervisor_regs.
That makes all of the riscv_cpu_vector_enabled checks return true for 0.7.1,
which afaik is correct.
> @@ -245,7 +250,9 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a,
> uint8_t seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> - return ldst_us_trans(a->rd, a->rs1, data, fn, s);
> + ret = ldst_us_trans(a->rd, a->rs1, data, fn, s);
> + mark_vs_dirty(s);
> + return ret;
Just push the mark_vs_dirty call into ldst_us_trans.
> @@ -382,7 +390,9 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a,
> uint8_t seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + ret = ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + mark_vs_dirty(s);
> + return ret;
Likewise.
> @@ -510,7 +521,9 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a,
> uint8_t seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + ret = ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + mark_vs_dirty(s);
> + return ret;
Likewise.
> @@ -632,7 +646,9 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a,
> uint8_t seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, NF, a->nf);
> - return ldff_trans(a->rd, a->rs1, data, fn, s);
> + ret = ldff_trans(a->rd, a->rs1, data, fn, s);
> + mark_vs_dirty(s);
Likewise.
> @@ -741,7 +758,9 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t
> seq)
> data = FIELD_DP32(data, VDATA, VM, a->vm);
> data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> data = FIELD_DP32(data, VDATA, WD, a->wd);
> - return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + ret = amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> + mark_vs_dirty(s);
> + return ret;
Likewise.
> @@ -911,9 +932,12 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn
> *gvec_fn,
>
> tcg_temp_free_i64(src1);
> tcg_temp_free(tmp);
> + mark_vs_dirty(s);
> return true;
> }
> - return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
> + ret = opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
> + mark_vs_dirty(s);
> + return ret;
Likewise. And more.
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 9632e79cf3..a806e33301 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -47,6 +47,7 @@ typedef struct DisasContext {
> bool virt_enabled;
> uint32_t opcode;
> uint32_t mstatus_fs;
> + uint32_t mstatus_vs;
Missing a change to riscv_tr_init_disas_context to initialize this.
r~
- [RFC 37/65] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions, (continued)
- [RFC 37/65] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions, frank . chang, 2020/07/10
- [RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions, frank . chang, 2020/07/10
- [RFC 03/65] target/riscv: fix return value of do_opivx_widen(), frank . chang, 2020/07/10
- [RFC 06/65] target/riscv: rvv-0.9: add vcsr register, frank . chang, 2020/07/10
- [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions, frank . chang, 2020/07/10
- [RFC 07/65] target/riscv: rvv-0.9: add vector context status, frank . chang, 2020/07/10
- [RFC 19/65] target/riscv: rvv-0.9: load/store whole register instructions, frank . chang, 2020/07/10
- [RFC 25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction, frank . chang, 2020/07/10
- [RFC 31/65] target/riscv: rvv-0.9: whole register move instructions, frank . chang, 2020/07/10
- [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), frank . chang, 2020/07/10
- [RFC 04/65] target/riscv: fix vill bit index in vtype register, frank . chang, 2020/07/10
- [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, frank . chang, 2020/07/10