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Re: [RFC 14/65] target/riscv: rvv-0.9: stride load and store instruction
From: |
Richard Henderson |
Subject: |
Re: [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions |
Date: |
Fri, 10 Jul 2020 11:15:30 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 |
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> # *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
> -vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
> -vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
> -vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
Again, something you can't do until 0.7.1 is not supported.
If you don't want to simultaneously support 0.7.1 and 0.9/1.0, then you should
simply remove 0.7.1 in the first patch, so that there's no confusion.
Is the rest of it mostly renaming? You should definitely expand on what you're
doing within each patch description. A description of what has changed in the
spec since 0.7.1 will help the reviewer validate that you've gotten all of the
corner cases.
I am going to stop reviewing this patch series now, as I expect that most of
the remaining patches will have similar comments.
r~
- [RFC 00/65] target/riscv: support vector extension v0.9, frank . chang, 2020/07/10
- [RFC 27/65] target/riscv: rvv-0.9: iota instruction, frank . chang, 2020/07/10
- [RFC 37/65] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions, frank . chang, 2020/07/10
- [RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions, frank . chang, 2020/07/10
- [RFC 03/65] target/riscv: fix return value of do_opivx_widen(), frank . chang, 2020/07/10
- [RFC 06/65] target/riscv: rvv-0.9: add vcsr register, frank . chang, 2020/07/10
- [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions, frank . chang, 2020/07/10
- Re: [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions,
Richard Henderson <=
- [RFC 07/65] target/riscv: rvv-0.9: add vector context status, frank . chang, 2020/07/10
- [RFC 19/65] target/riscv: rvv-0.9: load/store whole register instructions, frank . chang, 2020/07/10
- [RFC 25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction, frank . chang, 2020/07/10
- [RFC 31/65] target/riscv: rvv-0.9: whole register move instructions, frank . chang, 2020/07/10
- [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), frank . chang, 2020/07/10
- [RFC 04/65] target/riscv: fix vill bit index in vtype register, frank . chang, 2020/07/10