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Re: [RFC 07/65] target/riscv: rvv-0.9: add vector context status
From: |
Richard Henderson |
Subject: |
Re: [RFC 07/65] target/riscv: rvv-0.9: add vector context status |
Date: |
Fri, 10 Jul 2020 10:27:27 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 |
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> From: LIU Zhiwei <zhiwei_liu@c-sky.com>
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/cpu.h | 4 ++
> target/riscv/cpu_bits.h | 1 +
> target/riscv/cpu_helper.c | 13 ++++++
> target/riscv/csr.c | 25 ++++++++++-
> target/riscv/insn_trans/trans_rvv.inc.c | 57 +++++++++++++++++++++----
> target/riscv/translate.c | 32 ++++++++++++++
> 6 files changed, 123 insertions(+), 9 deletions(-)
BTW, I think this should be split.
One patch for the csr.c changes, another for the translate changes.
r~
- [RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions, (continued)
- [RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions, frank . chang, 2020/07/10
- [RFC 03/65] target/riscv: fix return value of do_opivx_widen(), frank . chang, 2020/07/10
- [RFC 06/65] target/riscv: rvv-0.9: add vcsr register, frank . chang, 2020/07/10
- [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions, frank . chang, 2020/07/10
- [RFC 07/65] target/riscv: rvv-0.9: add vector context status, frank . chang, 2020/07/10
- [RFC 19/65] target/riscv: rvv-0.9: load/store whole register instructions, frank . chang, 2020/07/10
- [RFC 25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction, frank . chang, 2020/07/10
- [RFC 31/65] target/riscv: rvv-0.9: whole register move instructions, frank . chang, 2020/07/10
- [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), frank . chang, 2020/07/10
- [RFC 04/65] target/riscv: fix vill bit index in vtype register, frank . chang, 2020/07/10
- [RFC 05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec, frank . chang, 2020/07/10