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[PATCH v2 22/25] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal
From: |
Bin Meng |
Subject: |
[PATCH v2 22/25] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value |
Date: |
Sat, 23 Jan 2021 18:40:13 +0800 |
From: Bin Meng <bin.meng@windriver.com>
All other peripherals' IRQs are in the format of decimal value.
Change SIFIVE_U_GEM_IRQ to be consistent.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
include/hw/riscv/sifive_u.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index de1464a2ce..2656b39808 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -127,7 +127,7 @@ enum {
SIFIVE_U_PDMA_IRQ6 = 29,
SIFIVE_U_PDMA_IRQ7 = 30,
SIFIVE_U_QSPI0_IRQ = 51,
- SIFIVE_U_GEM_IRQ = 0x35
+ SIFIVE_U_GEM_IRQ = 53
};
enum {
--
2.25.1
- Re: [PATCH v2 11/25] hw/sd: ssi-sd: Use macros for the dummy value and tokens in the transfer, (continued)
- [PATCH v2 13/25] hw/sd: sd: Allow single/multiple block write for SPI mode, Bin Meng, 2021/01/23
- [PATCH v2 14/25] hw/sd: sd.h: Cosmetic change of using spaces, Bin Meng, 2021/01/23
- [PATCH v2 15/25] hw/sd: Introduce receive_ready() callback, Bin Meng, 2021/01/23
- [PATCH v2 16/25] hw/sd: ssi-sd: Support single block write, Bin Meng, 2021/01/23
- [PATCH v2 19/25] hw/ssi: Add SiFive SPI controller support, Bin Meng, 2021/01/23
- [PATCH v2 23/25] docs/system: Sort targets in alphabetical order, Bin Meng, 2021/01/23
- [PATCH v2 25/25] docs/system: riscv: Add documentation for sifive_u machine, Bin Meng, 2021/01/23
- [PATCH v2 20/25] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash, Bin Meng, 2021/01/23
- [PATCH v2 22/25] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value,
Bin Meng <=
- [PATCH v2 21/25] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card, Bin Meng, 2021/01/23
- [PATCH v2 24/25] docs/system: Add RISC-V documentation, Bin Meng, 2021/01/23
- Re: [PATCH v2 00/25] hw/riscv: sifive_u: Add missing SPI support, Philippe Mathieu-Daudé, 2021/01/24