Re: [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access

qemu-riscv

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access

From:	Richard Henderson
Subject:	Re: [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access
Date:	Thu, 18 Mar 2021 07:25:22 -0600
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1

On 3/17/21 11:40 AM, Alistair Francis wrote:

          result = riscv_csrrw_debug(env, n - 32, &val,
                                     0, 0);
-        if (result == 0) {
+        if (result != RISCV_EXCP_NONE) {


This was intending == NONE.  I.e. no exception raised, let gdb proceed.


r~

[Prev in Thread]

Current Thread

[Next in Thread]

[PATCH v1 0/5] RISC-V: Convert the CSR access functions to use, Alistair Francis, 2021/03/17
- [PATCH v1 1/5] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/03/17
  - Re: [PATCH v1 1/5] target/riscv: Convert the RISC-V exceptions to an enum, Bin Meng, 2021/03/17
    - Re: [PATCH v1 1/5] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/03/19
- [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates, Alistair Francis, 2021/03/17
  - Re: [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates, Richard Henderson, 2021/03/17
    - Re: [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates, Alistair Francis, 2021/03/19
- [PATCH v1 3/5] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/03/17
- [PATCH v1 4/5] target/riscv: Use the RiscVException enum for CSR operations, Alistair Francis, 2021/03/17
- [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access, Alistair Francis, 2021/03/17
  - Re: [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access, Richard Henderson <=
    - Re: [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access, Alistair Francis, 2021/03/19

Prev by Date: Re: [PATCH v1 1/5] target/riscv: Convert the RISC-V exceptions to an enum
Next by Date: Re: [PATCH] target/riscv: Adjust privilege level for HLV(X)/HSV instructions
Previous by thread: [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access
Next by thread: Re: [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access
Index(es):
- Date
- Thread