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Re: [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access |
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Date: |
Fri, 19 Mar 2021 09:19:11 -0400 |
On Thu, Mar 18, 2021 at 9:25 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 3/17/21 11:40 AM, Alistair Francis wrote:
> > result = riscv_csrrw_debug(env, n - 32, &val,
> > 0, 0);
> > - if (result == 0) {
> > + if (result != RISCV_EXCP_NONE) {
>
> This was intending == NONE. I.e. no exception raised, let gdb proceed.
Good catch! Fixed.
Alistair
>
>
> r~
- [PATCH v1 1/5] target/riscv: Convert the RISC-V exceptions to an enum, (continued)
- [PATCH v1 1/5] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/03/17
- [PATCH v1 2/5] target/riscv: Use the RiscVException enum for CSR predicates, Alistair Francis, 2021/03/17
- [PATCH v1 3/5] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/03/17
- [PATCH v1 4/5] target/riscv: Use the RiscVException enum for CSR operations, Alistair Francis, 2021/03/17
- [PATCH v1 5/5] target/riscv: Use RiscVException enum for CSR access, Alistair Francis, 2021/03/17