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Re: [PATCH 02/13] target/riscv: Create RISCVMXL enumeration
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH 02/13] target/riscv: Create RISCVMXL enumeration |
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Date: |
Tue, 12 Oct 2021 09:28:31 +1000 |
On Fri, Oct 8, 2021 at 3:47 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Move the MXL_RV* defines to enumerators.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu_bits.h | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 999187a9ee..e248c6bf6d 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -364,9 +364,11 @@
> #define MISA32_MXL 0xC0000000
> #define MISA64_MXL 0xC000000000000000ULL
>
> -#define MXL_RV32 1
> -#define MXL_RV64 2
> -#define MXL_RV128 3
> +typedef enum {
> + MXL_RV32 = 1,
> + MXL_RV64 = 2,
> + MXL_RV128 = 3,
> +} RISCVMXL;
>
> /* sstatus CSR bits */
> #define SSTATUS_UIE 0x00000001
> --
> 2.25.1
>
>
- [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length, Richard Henderson, 2021/10/07
- [PATCH 02/13] target/riscv: Create RISCVMXL enumeration, Richard Henderson, 2021/10/07
- [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line, Richard Henderson, 2021/10/07
- [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/07
- [PATCH 07/13] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/07
- [PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Richard Henderson, 2021/10/07