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Re: [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cp
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From: |
Frédéric Pétrot |
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Subject: |
Re: [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl |
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Date: |
Wed, 13 Oct 2021 18:46:25 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 |
Hello,
Le 07/10/2021 à 19:47, Richard Henderson a écrit :
> Shortly, the set of supported XL will not be just 32 and 64,
> and representing that properly using the enumeration will be
> imperative.
>
> Two places, booting and gdb, intentionally use misa_mxl_max
> to emphasize the use of the reset value of misa.mxl, and not
> the current cpu state.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/cpu.h | 9 ++++++++-
> hw/riscv/boot.c | 2 +-
> semihosting/arm-compat-semi.c | 2 +-
> target/riscv/cpu.c | 24 ++++++++++++++----------
> target/riscv/cpu_helper.c | 12 ++++++------
> target/riscv/csr.c | 24 ++++++++++++------------
> target/riscv/gdbstub.c | 2 +-
> target/riscv/monitor.c | 4 ++--
> 8 files changed, 45 insertions(+), 34 deletions(-)
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> @@ -522,7 +522,7 @@ static RISCVException write_mstatus(CPURISCVState *env,
> int csrno,
>
> dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
> ((mstatus & MSTATUS_XS) == MSTATUS_XS);
> - if (riscv_cpu_is_32bit(env)) {
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
> } else {
> mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
I believe we miss the settings of the SXL and UXL fields that are needed
by cpu_get_xl
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9c0753bc8b..c4a479ddd2 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -526,6 +526,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int
csrno,
mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
} else {
mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
+ /* SXL and UXL fields are for now read only */
+ mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
+ mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
}
env->mstatus = mstatus;
Frédéric
--
+---------------------------------------------------------------------------+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |
+---------------------------------------------------------------------------+
- [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length, Richard Henderson, 2021/10/07
- [PATCH 02/13] target/riscv: Create RISCVMXL enumeration, Richard Henderson, 2021/10/07
- [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line, Richard Henderson, 2021/10/07
- [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/07
- Re: [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl,
Frédéric Pétrot <=
- [PATCH 07/13] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/07
- [PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Richard Henderson, 2021/10/07
- [PATCH 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/07
- [PATCH 12/13] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/07
- [PATCH 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen, Richard Henderson, 2021/10/07
- [PATCH 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64, Richard Henderson, 2021/10/07
- [PATCH 03/13] target/riscv: Split misa.mxl and misa.ext, Richard Henderson, 2021/10/07