Re: [PATCH 02/13] target/riscv: Create RISCVMXL enumeration

qemu-riscv

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH 02/13] target/riscv: Create RISCVMXL enumeration

From:	LIU Zhiwei
Subject:	Re: [PATCH 02/13] target/riscv: Create RISCVMXL enumeration
Date:	Wed, 13 Oct 2021 20:18:23 +0800
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0


On 2021/10/8 上午1:47, Richard Henderson wrote:

Move the MXL_RV* defines to enumerators.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>

Zhiwei

---
  target/riscv/cpu_bits.h | 8 +++++---
  1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187a9ee..e248c6bf6d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -364,9 +364,11 @@
  #define MISA32_MXL          0xC0000000
  #define MISA64_MXL          0xC000000000000000ULL

-#define MXL_RV32 1

-#define MXL_RV64            2
-#define MXL_RV128           3
+typedef enum {
+    MXL_RV32  = 1,
+    MXL_RV64  = 2,
+    MXL_RV128 = 3,
+} RISCVMXL;

/* sstatus CSR bits */

  #define SSTATUS_UIE         0x00000001

[Prev in Thread]

Current Thread

[Next in Thread]

[RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length, Richard Henderson, 2021/10/07
- [PATCH 02/13] target/riscv: Create RISCVMXL enumeration, Richard Henderson, 2021/10/07
  - Re: [PATCH 02/13] target/riscv: Create RISCVMXL enumeration, Alistair Francis, 2021/10/11
  - Re: [PATCH 02/13] target/riscv: Create RISCVMXL enumeration, LIU Zhiwei <=
- [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line, Richard Henderson, 2021/10/07
  - Re: [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line, Alistair Francis, 2021/10/07
  - Re: [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line, LIU Zhiwei, 2021/10/13
- [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/07
  - Re: [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Frédéric Pétrot, 2021/10/13
    - Re: [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/13
- [PATCH 07/13] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/07
- [PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Richard Henderson, 2021/10/07
  - Re: [PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI, LIU Zhiwei, 2021/10/13
- [PATCH 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/07

Prev by Date: Re: [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line
Next by Date: Re: [RFC PATCH v2 04/16] softmmu/qdev-monitor: add error handling in qdev_set_id
Previous by thread: Re: [PATCH 02/13] target/riscv: Create RISCVMXL enumeration
Next by thread: [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line
Index(es):
- Date
- Thread